R5F212DCSDFP资料

2023-09-26 来源：个人技术集锦

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R8C/2C Group, R8C/2D Group

RENESAS MCU

REJ03B0183-0100

Rev.1.00Feb 09, 2007

1.1

Overview

Features

The R8C/2C Group and R8C/2D Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space and is capable ofexecuting instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operationprocessing.

Power consumption is low, and the supported operating modes allow additional power control. These MCUs alsouse an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number ofsystem components.

Furthermore, the R8C/2D Group has on-chip data flash (1 KB × 2 blocks).

The difference between the R8C/2C Group and R8C/2D Group is only the presence or absence of data flash. Theirperipheral functions are the same.

1.1.1Applications

Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

1.1.2Specifications

Tables 1.1 and 1.2 outlines the Specifications for R8C/2C Group and Tables 1.3 and 1.4 outlines theSpecifications for R8C/2D Group.Table 1.1

ItemSpecifications for R8C/2C Group (1)

FunctionSpecificationCPUCentral processing R8C/Tiny series coreunit•Number of fundamental instructions: 89

•Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)•Multiplier: 16 bits × 16 bits → 32 bits

•Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits•Operation mode: Single-chip mode (address space: 1 Mbyte)

MemoryROM, RAMRefer to Table 1.5 Product List for R8C/2C Group.Power Supply Voltage detection •Power-on resetVoltage circuit•Voltage detection 3DetectionI/O PortsProgrammable I/O •Input-only: 2 pins

ports•CMOS I/O ports: 71, selectable pull-up resistor

•High current drive ports: 8

ClockClock generation 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), circuitsOn-chip oscillator (high-speed, low-speed)

(high-speed on-chip oscillator has a frequency adjustment function),XCIN clock oscillation circuit (32 kHz)

•Oscillation stop detection: XIN clock oscillation stop detection function•Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16•Low power consumption modes:

Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Interrupts•External: 5 sources, Internal: 23 sources, Software: 4 sources

•Priority levels: 7 levels

Watchdog Timer15 bits × 1 (with prescaler), reset start selectableTimerTimer RA8 bits × 1 (with 8-bit prescaler)Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode

Timer RB8 bits × 1 (with 8-bit prescaler)Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode

Timer RC16 bits × 1 (with 4 capture/compare registers)Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin)

Timer RD16 bits × 2 (with 4 capture/compare registers)Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period)

Timer RE8 bits × 1Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode

Timer RF16 bits × 1 (with capture/compare register pin and compare register pin)Input capture mode, output compare mode

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.2Specifications for R8C/2C Group (2)

SpecificationClock synchronous serial I/O/UART × 31 (shared with I2C-bus)

1 (shared with SSU)Hardware LIN: 1 (timer RA, UART0)10-bit resolution × 20 channels, includes sample and hold function, with sweep mode

8-bit resolution × 2 circuits•Programming and erasure voltage: VCC = 2.7 to 5.5 V•Programming and erasure endurance: 100 times•Program security: ROM code protect, ID code check

•Debug functions: On-chip debug, on-board flash rewrite functionf(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))0.65 µA (VCC = 3.0 V, stop mode)-20 to 85°C (N version)-40 to 85°C (D version)(2)80-pin LQFPPackage code: PLQP0080KB-A (previous code: 80P6Q-A)

ItemFunctionSerial UART0, UART1, InterfaceUART2

Clock Synchronous Serial I/O with Chip Select (SSU)I2C bus(1)LIN ModuleA/D ConverterD/A ConverterFlash MemoryOperating Frequency/Supply Voltage

Current consumptionOperating Ambient TemperaturePackageNOTES:

1.I2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D version if D version functions are to be used.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.3

ItemSpecifications for R8C/2D Group (1)

FunctionSpecificationCPUCentral processing R8C/Tiny series coreunit•Number of fundamental instructions: 89

•Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)•Multiplier: 16 bits × 16 bits → 32 bits

•Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits•Operation mode: Single-chip mode (address space: 1 Mbyte)

MemoryROM, RAMRefer to Table 1.6 Product List for R8C/2D Group.Power Supply Voltage detection •Power-on resetVoltage circuit•Voltage detection 3DetectionI/O PortsProgrammable I/O •Input-only: 2 pinsports•CMOS I/O ports: 71, selectable pull-up resistor

•High current drive ports: 8

ClockClock generation 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), circuitsOn-chip oscillator (high-speed, low-speed)

(high-speed on-chip oscillator has a frequency adjustment function),XCIN clock oscillation circuit (32 kHz)

•Oscillation stop detection: XIN clock oscillation stop detection function•Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16•Low power consumption modes:

Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Interrupts•External: 5 sources, Internal: 23 sources, Software: 4 sources•Priority levels: 7 levels

Timer RC16 bits × 1 (with 4 capture/compare registers)Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin)

Timer RD16 bits × 2 (with 4 capture/compare registers)Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase

waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period)

Timer RE8 bits × 1Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode

Timer RF16 bits × 1 (with capture/compare register pin and compare register pin)Input capture mode, output compare mode

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.4Specifications for R8C/2D Group (2)

SpecificationClock synchronous serial I/O/UART × 31 (shared with I2C-bus)

1 (shared with SSU)Hardware LIN: 1 (timer RA, UART0)10-bit resolution × 20 channels, includes sample and hold function, with sweep mode

8-bit resolution × 2 circuits•Programming and erasure voltage: VCC = 2.7 to 5.5 V•Programming and erasure endurance: 10,000 times (data flash)

1,000 times (program ROM)

•Program security: ROM code protect, ID code check

2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))0.65 µA (VCC = 3.0 V, stop mode)-20 to 85°C (N version)-40 to 85°C (D version)(2)80-pin LQFPPackage code: PLQP0080KB-A (previous code: 80P6Q-A)

ItemFunctionSerial UART0, UART1, InterfaceUART2

Clock Synchronous Serial I/O with Chip Select (SSU)I2C bus(1)LIN ModuleA/D ConverterD/A ConverterFlash MemoryOperating Frequency/Supply Voltage

Current consumptionOperating Ambient TemperaturePackageNOTES:

1.I2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D version if D version functions are to be used.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

1.2Product List

Table 1.5 lists Product List for R8C/2C Group, Figure 1.1 shows a Part Number, Memory Size, and Package ofR8C/2C Group, Table 1.6 lists Product List for R8C/2D Group, and Figure 1.2 shows a Part Number, Memory Size,and Package of R8C/2D Group.Table 1.5

Product List for R8C/2C Group

ROM Capacity48 Kbytes64 Kbytes96 Kbytes128 Kbytes48 Kbytes64 Kbytes96 Kbytes128 Kbytes

RAM Capacity2.5 Kbytes3 Kbytes7 Kbytes7.5 Kbytes2.5 Kbytes3 Kbytes7 Kbytes7.5 Kbytes

Package TypePLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-A

Current of Feb. 2007RemarksN version

Part No.

R5F212C7SNFPR5F212C8SNFPR5F212CASNFP (D)R5F212CCSNFP (D)R5F212C7SDFP (D)R5F212C8SDFP (D)R5F212CASDFP (D)R5F212CCSDFP (D)(D): Under development

D version

Part No. R 5 F 21 2C 7 S N FPPackage type:FP: PLQP0080KB-A (0.5 mm pin-pitch, 12 mm square body)ClassificationN: Operating ambient temperature -20°C to 85°CD: Operating ambient temperature -40°C to 85°CS: Low-voltage versionROM capacity7: 48 KB8: 64 KBA: 96 KBC: 128 KBR8C/2C GroupR8C/Tiny SeriesMemory typeF: Flash memoryRenesas MCURenesas semiconductorFigure 1.1Part Number, Memory Size, and Package of R8C/2C GroupRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.6Product List for R8C/2D Group

RAM Capacity2.5 Kbytes3 Kbytes7 Kbytes7.5 Kbytes2.5 Kbytes3 Kbytes7 Kbytes7.5 Kbytes

Current of Feb. 2007

Package TypePLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-APLQP0080KB-A

RemarksN version

ROM Capacity

Program ROMData flash

R5F212D7SNFP48 Kbytes1 Kbyte × 2R5F212D8SNFP64 Kbytes1 Kbyte × 2R5F212DASNFP (D)96 Kbytes1 Kbyte × 2R5F212DCSNFP (D)128 Kbytes1 Kbyte × 2R5F212D7SDFP(D)48 Kbytes1 Kbyte × 2R5F212D8SDFP(D)64 Kbytes1 Kbyte × 2R5F212DASDFP(D)96 Kbytes1 Kbyte × 2R5F212DCSDFP (D)128 Kbytes1 Kbyte × 2

Part No.

(D): Under development

D version

Part No. R 5 F 21 2D 7 S N FPPackage type:FP: PLQP0080KB-A (0.5 mm pin-pitch, 12 mm square body)ClassificationN: Operating ambient temperature -20°C to 85°CD: Operating ambient temperature -40°C to 85°CS: Low-voltage versionROM capacity7: 48 KB8: 64 KBA: 96 KBC: 128 KBR8C/2D GroupR8C/Tiny SeriesMemory typeF: Flash memoryRenesas MCURenesas semiconductorFigure 1.2Part Number, Memory Size, and Package of R8C/2D GroupRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

1.3 Block Diagram

Figure 1.3 shows a Block Diagram.

8888328I/O portsPeripheral functionsTimersTimer RA (8 bits × 1)Timer RB (8 bits × 1)Timer RC (16 bits × 1)Timer RD (16 bits × 2)Timer RE (8 bits × 1)Timer RF (16 bits × 1)Port P0Port P1Port P2Port P3Port P4Port P5Port P6UART orclock synchronous serial I/O(8 bits × 3)I2C bus or SSU(8 bits × 1)System clock generationcircuitXIN-XOUTHigh-speed on-chip oscillatorLow-speed on-chip oscillatorXCIN-XCOUT8Port P78LIN modulePort P88Watchdog timer(15 bits)Port P9A/D converter(10 bits × 20 channels)D/A converter(8 bits × 2)4R8C/Tiny Series CPU coreR0HR1HR2R3A0A1FBR0LR1LSBUSPISPINTBPCFLGMemoryROM(1)RAM(2)MultiplierNOTES:1. ROM size varies with MCU type.2. RAM size varies with MCU type.Figure 1.3Block DiagramRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

1.4Pin Assignment

Figure 1.4 shows Pin Assignment (Top View). Tables 1.7 and 1.8 outlines the Pin Name Information by PinNumber.

P6_5/(CLK1)/CLK2(2)P6_7/INT3/RXD1P6_6/INT2/TXD1P1_2/Kl2/AN10P1_3/Kl3/AN11P8_0/TRFO006059585756555453525150494847464544434241P8_1/TRFO01P1_0/Kl0/AN8P1_1/Kl1/AN9P3_2/(INT2)(2)P3_6/(INT1)(2)P3_0/TRAOP3_1/TRBOP6_0/TREOP6_4/RXD2P6_3/TXD2P7_5/AN17P7_6/AN18P7_7/AN19P4_5/INT0P7_4/AN16P7_3/AN15P7_2/AN14P7_1/AN13P7_0/AN12P0_0/AN7P0_1/AN6P0_2/AN5P0_3/AN4P0_4/AN3P6_2P6_1P0_5/AN2/CLK1P0_6/AN1/DA0VSS/AVSSP0_7/AN0/DA1VREFVCC/AVCCP3_7/SSOP3_5/SCL/SSCK616263646566676869707172737475767778798012345678910111213141516171819204039383736353433P8_2/TRFO02P8_3/TRFO10/TRFIP8_4/TRFO11P8_5/TRFO12P8_6P8_7P1_4/TXD0P1_5/RXD0/(TRAIO)/(INT1)(2)P1_6/CLK0P1_7/TRAIO/INT1P2_0/TRDIOA0/TRDCLKP2_1/TRDIOB0P2_2/TRDIOC0P2_3/TRDIOD0P2_4/TRDIOA1P2_5/TRDIOB1P2_6/TRDIOC1P2_7/TRDIOD1P9_0P9_1R8C/2C GroupR8C/2D GroupPLQP0080KB-A(80P6Q-A) (top view)323130292827262524232221P4_7/XOUT(1)P3_3/SSIP5_7P5_6P5_5P9_3P4_4/XCOUTRESETMODEVSS/AVSSP3_4/SDA/SCSP5_2/TRCIOBNOTES:1. P4_7/XOUT are an input-only port.2. Can be assigned to the pin in parentheses by a program.3. Confirm the pin 1 position on the package by referring to the package dimensions.Figure 1.4Pin Assignment (Top View)Rev.1.00Feb 09, 2007REJ03B0183-0100

Page 9 of 55

P5_1/TRCIOA/TRCTRGP5_0/TRCCLKVCC/AVCCP4_3/XCINP4_6/XINP5_4/TRCIODP5_3/TRCIOCP9_2元器件交易网www.cecb2b.com

R8C/2C Group, R8C/2D Group

1. Overview

Table 1.7Pin Name Information by Pin Number (1)

PortP3_3P3_4P5_7P5_6P5_5

MODEXCINXCOUTRESETXOUTVSS/AVSS

XINVCC/AVCC

P4_3P4_4P4_7P4_6P5_4P5_3P5_2P5_1P5_0P9_3P9_2P9_1P9_0P2_7P2_6P2_5P2_4P2_3P2_2P2_1P2_0P1_7P1_6P1_5P1_4P8_7P8_6P8_5P8_4P8_3P8_2P8_1P8_0P6_0P4_5P6_6

TRCIODTRCIOCTRCIOB

TRCIOA/TRCTRG

TRCCLK

I/O Pin Functions for of Peripheral Modules

Serial

TimerSSUI2C bus

Interface

SSI

SDASCS

A/D Converter,D/A ConverterPin

Control Pin

Number123456789101112131415161718192021222324252627282930313233343536373839404142434445

Interrupt

INT1(INT1)(1)

TRDIOD1TRDIOC1TRDIOB1TRDIOA1TRDIOD0TRDIOC0TRDIOB0

TRDIOA0/ TRDCLK

TRAIO

(TRAIO)(1)

CLK0RXD0TXD0

INT0INT2

TRFO12TRFO11TRFO10/TRFITRFO02TRFO01TRFO00TREOINT0

TXD1

NOTE:

1.Can be assigned to the pin in parentheses by a program.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.8Pin Name Information by Pin Number (2)

PortP6_7P6_5P6_4P6_3P3_1P3_0P3_6P3_2P1_3P1_2P1_1P1_0P7_7P7_6P7_5P7_4P7_3P7_2P7_1P7_0P0_0P0_1P0_2P0_3P0_4P6_2P6_1P0_5P0_6

VSS/AVSS

P0_7

VREFVCC/AVCC

P3_7P3_5

SSOSSCK

SCL

AN0/DA1

(INT1)(1)(INT2)(1)KI3KI2KI1KI0

AN11AN10AN9AN8AN19AN18AN17AN16AN15AN14AN13AN12AN7AN6AN5AN4AN3

I/O Pin Functions for of Peripheral Modules

Serial

TimerSSUI2C bus

Interface

RXD1(CLK1)(1)/CLK2RXD2TXD2

TRBOTRAO

A/D Converter,D/A ConverterPin

Control Pin

Number4647484950515253545556575859606162636465666768697071727374757677787980

InterruptINT3

CLK1

AN2AN1/DA0

NOTE:

1.Can be assigned to the pin in parentheses by a program.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

1.5Pin Functions

Pin Functions (1)

Pin NameVCC, VSSAVCC, AVSSRESETMODEXINXOUTXCINXCOUTINT0 to INT3KI0 to KI3TRAIOTRAOTRBOTRCCLKTRCTRG

TRCIOA, TRCIOB,TRCIOC, TRCIOD

I/O Type−−IIIOIOIII/OOOIII/OI/O

Description

Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.Input “L” on this pin resets the MCU.Connect this pin to VCC via a resistor.

These pins are provided for XIN clock generation circuit I/O.Connect a ceramic resonator or a crystal oscillator betweenthe XIN and XOUT pins(1). To use an external clock, input it tothe XIN pin and leave the XOUT pin open.

These pins are provided for XCIN clock generation circuit I/O.Connect a crystal oscillator between the XCIN and XCOUTpins(1). To use an external clock, input it to the XCIN pin andleave the XCOUT pin open.

INT interrupt input pins.

INT0 is timer RD input pin. INT1 is timer RA input pin.Key input interrupt input pinsTimer RA I/O pinTimer RA output pinTimer RB output pinExternal clock input pinExternal trigger input pinTimer RC I/O pinsTimer RD I/O pins

Tables 1.9 and 1.10 list Pin Functions.Table 1.9

Item

Power supply inputAnalog power supply inputReset inputMODEXIN clock inputXIN clock outputXCIN clock inputXCIN clock outputINT interrupt inputKey input interruptTimer RATimer RBTimer RC

Timer RD

TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1TRDCLKTREOTRFI

TRFO00 to TRFO02, TRFO10 to TRFO12

IOIOI/OIOI/OI/OI/OI/OI/OI/OI

External clock input pinDivided clock output pinTimer RF input pinTimer RF output pinsTransfer clock I/O pinsSerial data input pinsSerial data output pinsClock I/O pinData I/O pinData I/O pin

Chip-select signal I/O pinClock I/O pinData I/O pin

Reference voltage input pin to A/D converter and D/Aconverter

Timer RETimer RF

Serial interfaceCLK0, CLK1, CLK2RXD0, RXD1, RXD2TXD0, TXD1, TXD2

I2C busSSU

SCLSDASSISCSSSCKSSO

Reference voltage input

VREF

I: InputO: OutputI/O: Input and outputNOTE:

1.Refer to the oscillator manufacturer for oscillation characteristics.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

1. Overview

Table 1.10

Item

A/D converterD/A converterI/O port

Pin Functions (2)

Pin NameAN0 to AN19DA0 to DA1P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_3 to P4_5, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3P4_6, P4_7

O: Output

I/O TypeIOI/O

Description

Analog input pins to A/D converterD/A converter output pins

CMOS I/O ports. Each port has an I/O select directionregister, allowing each pin in the port to be directed for inputor output individually.

Any port set to input can be set to use a pull-up resistor or notby a program.

P2_0 to P2_7 also function as LED drive ports.

Input portI: Input

IInput-only ports

I/O: Input and output

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

2. Central Processing Unit (CPU)

2.Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure aregister bank. There are two sets of register bank. b31b15b8b7b0R2R3R0H (high-order of R0)R0L (low-order of R0)R1H (high-order of R1)R1L (low-order of R1)Data registers(1)R2R3A0A1FBb19b15b0Address registers(1)Frame base register(1)INTBHINTBLInterrupt table registerThe 4 high order bits of INTB are INTBH andthe 16 low order bits of INTB are INTBL.b19b0PCProgram counterb15b0USPISPSBb15b0User stack pointerInterrupt stack pointerStatic base registerFLGb15b8b7b0Flag registerIPLUIOBSZDCCarry flagDebug flagZero flagSign flagRegister bank select flagOverflow flagInterrupt enable flagStack pointer select flagReserved bitProcessor interrupt priority levelReserved bitNOTE:1. These registers comprise a register bank. There are two register banks.Figure 2.1CPU RegistersRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

2. Central Processing Unit (CPU)

2.1Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be splitinto high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L areanalogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 isanalogous to R2R0.

2.2Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is alsoused for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-bit address register (A1A0).

2.3Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.

2.5Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch betweenUSP and ISP.

2.7Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5Register Bank Select Flag (B)

2.8.6Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

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R8C/2C Group, R8C/2D Group

2. Central Processing Unit (CPU)

2.8.7Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0when an interrupt request is acknowledged.

2.8.8Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of softwareinterrupt numbers 0 to 31 is executed.

2.8.9Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10Reserved Bit

If necessary, set to 0. When read, the content is undefined.

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R8C/2C Group, R8C/2D Group

3. Memory

3.1

Memory

R8C/2C Group

Figure 3.1 is a Memory Map of R8C/2C Group. The R8C/2C group has 1 Mbyte of address space from addresses00000h to FFFFFh.

The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internalROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of eachinterrupt routine.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internalRAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but alsofor calling subroutines and as stacks when interrupt requests are acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function controlregisters are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future useand cannot be accessed by users.

00000hSFR(Refer to 4. SpecialFunction Registers(SFRs))002FFh00400hInternal RAM0XXXXh03000hInternal RAM0WWWWh0FFDChUndefined instructionOverflowBRK instructionAddress matchSingle stepWatchdog timer, oscillation stop detection, voltage monitor0YYYYhInternal ROM(program ROM)0FFFFhZZZZZhFFFFFhInternal ROM(program ROM)Expanded area0FFFFh(Reserved)(Reserved)ResetNOTE:1. The blank regions are reserved. Do not access locations in these regions.Internal ROMPart NumberR5F212C7SNFP, R5F212C7SDFPR5F212C8SNFP, R5F212C8SDFPSize48 Kbytes64 KbytesAddress 0YYYYhAddress ZZZZZh04000h04000h04000h04000h−13FFFh1BFFFh23FFFhSize2.5 Kbytes3 Kbytes7 Kbytes7.5 KbytesInternal RAMAddress 0XXXXhAddress 0WWWWh00DFFh00FFFh011FFh011FFh−−03DFFh03FFFhR5F212CASNFP, R5F212CASDFP96 KbytesR5F212CCSNFP, R5F212CCSDFP128 KbytesFigure 3.1Memory Map of R8C/2C GroupRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

3. Memory

3.2R8C/2D Group

Figure 3.2 is a Memory Map of R8C/2D Group. The R8C/2D group has 1 Mbyte of address space from addresses00000h to FFFFFh.

The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of eachinterrupt routine.

The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.

The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyteinternal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data butalso for calling subroutines and as stacks when interrupt requests are acknowledged.

00000h002FFh00400h(Refer to 4. SpecialFunction Registers(SFRs))SFRInternal RAM0XXXXh02400h02BFFh03000hInternal ROM(data flash)(1)0FFDChInternal RAM0WWWWhUndefined instructionOverflowBRK instructionAddress matchSingle stepWatchdog timer, oscillation stop detection, voltage monitor0YYYYhInternal ROM(program ROM)0FFFFhZZZZZhFFFFFhInternal ROM(program ROM)Expanded area0FFFFh(Reserved)(Reserved)ResetNOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions.Part NumberInternal ROMSizeAddress 0YYYYhAddress ZZZZZh04000h04000h04000h04000h−13FFFh1BFFFh23FFFhSize2.5 Kbytes3 Kbytes7 Kbytes7.5 KbytesInternal RAMAddress 0XXXXhAddress 0WWWWh00DFFh00FFFh011FFh011FFh−−03DFFh03FFFhR5F212D7SNFP, R5F212D7SDFP48 KbytesR5F212D8SNFP, R5F212D8SDFP64 KbytesR5F212DASNFP, R5F212DASDFP96 KbytesR5F212DCSNFP, R5F212DCSDFP128 KbytesFigure 3.2Memory Map of R8C/2D GroupRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

4.Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the specialfunction registers.Table 4.1

Address0000h0001h0002h0003h0004h0005h0006h0007h0008h0009h000Ah000Bh000Ch000Dh000Eh000Fh0010h0011h0012h0013h0014h0015h0016h0017h0018h0019h001Ah001Bh001Ch001Dh001Eh001Fh0020h0021h0022h0023h0024h0025h0026h0027h0028h0029h002Ah002Bh0030h0031h0032h0033h0034h0035h0036h0037h0038hSFR Information (1)(1)

RegisterSymbolAfter resetProcessor Mode Register 0Processor Mode Register 1System Clock Control Register 0System Clock Control Register 1Module Operation Enable RegisterProtect RegisterOscillation Stop Detection RegisterWatchdog Timer Reset RegisterWatchdog Timer Start RegisterWatchdog Timer Control RegisterAddress Match Interrupt Register 0PM0PM1CM0CM1MSTCRPRCROCDWDTRWDTSWDCRMAD000h00h01101000b00100000b00h00h00000100bXXhXXh00X11111b00h00h00h00h00h00h00h

Address Match Interrupt Enable RegisterAddress Match Interrupt Register 1AIERRMAD1Count Source Protection Mode RegisterCSPR00h10000000b(6)

High-Speed On-Chip Oscillator Control Register 0High-Speed On-Chip Oscillator Control Register 1High-Speed On-Chip Oscillator Control Register 2FRA0FRA1FRA200hWhen shipping00hClock Prescaler Reset FlagCPSRF00hHigh-Speed On-Chip Oscillator Control Register 6FRA6 When ShippingVoltage Detection Register 1(2)Voltage Detection Register 2(2)VCA1VCA200001000b00h(3)00100000b(4)

Voltage Monitor 1 Circuit Control Register(5)Voltage Monitor 2 Circuit Control Register(5)Voltage Monitor 0 Circuit Control Register(2)VW1CVW2CVW0C00001000b 00h0000X000b(3)0100X001b(4)

0039h003Ah003Bh003Ch003Dh003Eh003FhX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.

2.Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.3.The LVD0ON bit in the OFS register is set to 1 and hardware reset.

4.Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.5.Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.6.The CSPROINI bit in the OFS register is set to 0.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.2

Address0040h0041h0042h0043h0044h0045h0046h0047h0048h0049h004Ah004Bh004Ch004Dh004Eh004Fh0050h0051h0052h0053h0054h0055h0056h0057h0058h0059h005Ah005Bh005Ch005Dh005Eh005Fh0060h0061h0062h0063h0064h0065h0066h0067h0068h0069h006Ah006Bh006Ch006Dh006Eh006Fh0070h0071h0072h0073h0074h0075h0076h0077h0078h0079h007Ah007Bh007Ch007Dh007Eh007FhSFR Information (2)(1)

RegisterSymbolAfter resetTimer RC Interrupt Control RegisterTimer RD0 Interrupt Control RegisterTimer RD1 Interrupt Control RegisterTimer RE Interrupt Control RegisterUART2 Transmit Interrupt Control RegisterUART2 Receive Interrupt Control RegisterKey Input Interrupt Control RegisterSSU/IIC Interrupt Control Register(2)Compare 1 Interrupt Control RegisterUART0 Transmit Interrupt Control RegisterUART0 Receive Interrupt Control RegisterUART1 Transmit Interrupt Control RegisterUART1 Receive Interrupt Control RegisterINT2 Interrupt Control RegisterTimer RA Interrupt Control RegisterTimer RB Interrupt Control RegisterINT1 Interrupt Control RegisterINT3 Interrupt Control RegisterTimer RF Interrupt Control RegisterCompare 0 Interrupt Control RegisterINT0 Interrupt Control RegisterA/D Conversion Interrupt Control RegisterCapture Interrupt Control RegisterTRCICTRD0ICTRD1ICTREICS2TICS2RICKUPICSSUIC / IICICCMP1ICS0TICS0RICS1TICS1RICINT2ICTRAICTRBICINT1ICINT3ICTRFICCMP0ICINT0ICADICCAPICXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXX00X000bXXXXX000bXXXXX000bXX00X000bXX00X000bXXXXX000bXXXXX000bXX00X000bXXXXX000bXXXXX000bX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.3

Address0080h0081h0082h0083h0084h0085h0086h0087h0088h0089h008Ah008Bh008Ch008Dh008Eh008Fh0090h0091h0092h0093h0094h0095h0096h0097h0098h0099h009Ah009Bh009Ch009Dh009Eh009Fh00A0h00A1h00A2h00A3h00A4h00A5h00A6h00A7h00A8h00A9h00AAh00ABh00ACh00ADh00AEh00AFh00B0h00B1h00B2h00B3h00B4h00B5h00B6h00B7h00B8h00B9h00BAh00BBh00BCh00BDh00BEh00BFh

SFR Information (3)(1)

RegisterSymbolAfter resetUART0 Transmit/Receive Mode RegisterUART0 Bit Rate RegisterUART0 Transmit Buffer RegisterUART0 Transmit/Receive Control Register 0UART0 Transmit/Receive Control Register 1UART0 Receive Buffer RegisterUART1 Transmit/Receive Mode RegisterUART1 Bit Rate RegisterUART1 Transmit Buffer RegisterUART1 Transmit/Receive Control Register 0UART1 Transmit/Receive Control Register 1UART1 Receive Buffer RegisterU0MRU0BRGU0TBU0C0U0C1U0RBU1MRU1BRGU1TBU1C0U1C1U1RB00hXXhXXhXXh

00001000b00000010bXXhXXh00hXXhXXhXXh

00001000b00000010bXXhXXh

SS Control Register H / IIC bus Control Register 1(2)SS Control Register L / IIC bus Control Register 2(2)SS Mode Register / IIC bus Mode Register(2)SS Enable Register / IIC bus Interrupt Enable Register(2)SS Status Register / IIC bus Status Register(2)SS Mode Register 2 / Slave Address Register(2)SS Transmit Data Register / IIC bus Transmit Data Register(2)SS Receive Data Register / IIC bus Receive Data Register(2)SSCRH / ICCR1SSCRL / ICCR2SSMR / ICMRSSER / ICIERSSSR / ICSRSSMR2 / SARSSTDR / ICDRTSSRDR / ICDRR00h01111101b00011000b00h00h / 0000X000b00hFFhFFhX: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.4

Address00C0h00C1h00C2h00C3h00C4h00C5h00C6h00C7h00C8h00C9h00CAh00CBh00CCh00CDh00CEh00CFh00D0h00D1h00D2h00D3h00D4h00D5h00D6h00D7h00D8h00D9h00DAh00DBh00DCh00DDh00DEh00DFh00E0h00E1h00E2h00E3h00E4h00E5h00E6h00E7h00E8h00E9h00EAh00EBh00ECh00EDh00EEh00EFh00F0h00F1h00F2h00F3h00F4h00F5h00F6h00F7h00F8h00F9h00FAh00FBh00FCh00FDh00FEh00FFhSFR Information (4)(1)

RegisterSymbolAfter resetD/A Register 0D/A Register 1D/A Control RegisterDA0DA1DACON00h00h00hPort P0 RegisterPort P1 RegisterPort P0 Direction RegisterPort P1 Direction RegisterPort P2 RegisterPort P3 RegisterPort P2 Direction RegisterPort P3 Direction RegisterPort P4 RegisterPort P5 RegisterPort P4 Direction RegisterPort P5 Direction RegisterPort P6 RegisterPort P6 Direction RegisterP0P1PD0PD1P2P3PD2PD3P4P5PD4PD5P6PD6XXhXXh00h00hXXhXXh00h00hXXhXXh00h00hXXh00hPort P2 Drive Capacity Control RegisterUART1 Function Select RegisterP2DRRU1SR00h00hPort Mode RegisterExternal Input Enable RegisterINT Input Filter Select RegisterKey Input Enable RegisterPull-Up Control Register 0Pull-Up Control Register 1PMRINTENINTFKIENPUR0PUR100h00h00h00h00hXX000000bX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.5

Address0100h0101h0102h0103h0104h0105h0106h0107h0108h0109h010Ah010Bh010Ch010Dh010Eh010Fh0110h0111h0112h0113h0114h0115h0116h0117h0118h0119h011Ah011Bh011Ch011Dh011Eh011Fh0120h0121h0122h0123h0124h0125h0126h0127h0128h0129h012Ah012Bh012Ch012Dh012Eh012Fh0130h0131h0132h0133h0134h0135h0136h0137h0138h0139h013Ah013Bh013Ch013Dh013Eh013FhNOTE:

SFR Information (5)(1)

RegisterTimer RA Control RegisterTimer RA I/O Control RegisterTimer RA Mode RegisterTimer RA Prescaler RegisterTimer RA RegisterLIN Control Register 2LIN Control RegisterLIN Status RegisterTimer RB Control RegisterTimer RB One-Shot Control RegisterTimer RB I/O Control RegisterTimer RB Mode RegisterTimer RB Prescaler RegisterTimer RB Secondary RegisterTimer RB Primary RegisterSymbolTRACRTRAIOCTRAMRTRAPRETRALINCR2LINCRLINSTTRBCRTRBOCRTRBIOCTRBMRTRBPRETRBSCTRBPRAfter reset00h00h00hFFhFFh00h00h00h00h00h00h00hFFhFFhFFhTimer RE Second Data Register / Counter Data RegisterTimer RE Minute Data Register / Compare Data RegisterTimer RE Hour Data RegisterTimer RE Day of Week Data RegisterTimer RE Control Register 1Timer RE Control Register 2Timer RE Clock Source Select Register Timer RC Mode RegisterTimer RC Control Register 1Timer RC Interrupt Enable RegisterTimer RC Status RegisterTimer RC I/O Control Register 0Timer RC I/O Control Register 1Timer RC CounterTimer RC General Register ATimer RC General Register BTimer RC General Register CTimer RC General Register DTimer RC Control Register 2Timer RC Digital Filter Function Select RegisterTimer RC Output Master Enable RegisterTRESECTREMINTREHRTREWKTRECR1TRECR2TRECSRTRCMRTRCCR1TRCIERTRCSRTRCIOR0TRCIOR1TRCTRCGRATRCGRBTRCGRCTRCGRDTRCCR2TRCDFTRCOER00h00h00h00h00h00h00001000b01001000b00h01110000b01110000b10001000b10001000b00h00hFFhFFhFFhFFhFFhFFhFFhFFh

00011111b00h01111111bTimer RD Start RegisterTimer RD Mode RegisterTimer RD PWM Mode RegisterTimer RD Function Control RegisterTimer RD Output Master Enable Register 1Timer RD Output Master Enable Register 2Timer RD Output Control RegisterTimer RD Digital Filter Function Select Register 0Timer RD Digital Filter Function Select Register 1TRDSTRTRDMRTRDPMRTRDFCRTRDOER1TRDOER2TRDOCRTRDDF0TRDDF111111100b00001110b10001000b10000000bFFh01111111b00h00h00hThe blank regions are reserved. Do not access locations in these regions

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.6

Address0140h0141h0142h0143h0144h0145h0146h0147h0148h0149h014Ah014Bh014Ch014Dh014Eh014Fh0150h0151h0152h0153h0154h0155h0156h0157h0158h0159h015Ah015Bh015Ch015Dh015Eh015Fh0160h0161h0162h0163h0164h0165h0166h0167h0168h0169h016Ah016Bh016Ch016Dh016Eh016Fh0170h0171h0172h0173h0174h0175h0176h0177h0178h0179h017Ah017Bh017Ch017Dh017Eh017FhSFR Information (6)(1)

RegisterTimer RD Control Register 0Timer RD I/O Control Register A0Timer RD I/O Control Register C0Timer RD Status Register 0Timer RD Interrupt Enable Register 0Timer RD PWM Mode Output Level Control Register 0Timer RD Counter 0Timer RD General Register A0Timer RD General Register B0Timer RD General Register C0Timer RD General Register D0Timer RD Control Register 1Timer RD I/O Control Register A1Timer RD I/O Control Register C1Timer RD Status Register 1Timer RD Interrupt Enable Register 1Timer RD PWM Mode Output Level Control Register 1Timer RD Counter 1Timer RD General Register A1Timer RD General Register B1Timer RD General Register C1Timer RD General Register D1UART2 Transmit/Receive Mode RegisterUART2 Bit Rate Register

UART2 Transmit Buffer RegisterUART2 Transmit/Receive Control Register 0UART2 Transmit/Receive Control Register 1UART2 Receive Buffer RegisterSymbolTRDCR0TRDIORA0TRDIORC0TRDSR0TRDIER0TRDPOCR0TRD0TRDGRA0TRDGRB0TRDGRC0TRDGRD0TRDCR1TRDIORA1TRDIORC1TRDSR1TRDIER1TRDPOCR1TRD1TRDGRA1TRDGRB1TRDGRC1TRDGRD1U2MRU2BRGU2TBU2C0U2C1U2RBAfter reset00h10001000b10001000b11000000b11100000b11111000b00h00hFFhFFhFFhFFhFFhFFhFFhFFh00h10001000b10001000b11000000b11100000b11111000b00h00hFFhFFhFFhFFhFFhFFhFFhFFh00hXXhXXhXXh

00001000b00000010bXXhXXh

X: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.7

Address0180h0181h0182h0183h0184h0185h0186h0187h0188h0189h018Ah018Bh018Ch018Dh018Eh018Fh0190h0191h0192h0193h0194h0195h0196h0197h0198h0199h019Ah019Bh019Ch019Dh019Eh019Fh01A0h01A1h01A2h01A3h01A4h01A5h01A6h01A7h01A8h01A9h01AAh01ABh01ACh01ADh01AEh01AFh01B0h01B1h01B2h01B3h01B4h01B5h01B6h01B7h01B8h01B9h01BAh01BBh01BCh01BDh01BEh01BFhSFR Information (7)(1)

RegisterSymbolAfter resetFlash Memory Control Register 4Flash Memory Control Register 1Flash Memory Control Register 0FMR4FMR1FMR001000000b1000000Xb00000001bX: UndefinedNOTE:

1.The blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.8

Address01C0h01C1h01C2h01C3h01C4h01C5h01C6h01C7h01C8h01C9h01CAh01CBh01CCh01CDh01CEh01CFh01D0h01D1h01D2h01D3h01D4h01D5h01D6h01D7h01D8h01D9h01DAh01DBh01DCh01DDh01DEh01DFh01E0h01E1h01E2h01E3h01E4h01E5h01E6h01E7h01E8h01E9h01EAh01EBh01ECh01EDh01EEh01EFh01F0h01F1h01F2h01F3h01F4h01F5h01F6h01F7h01F8h01F9h01FAh01FBh01FCh01FDh01FEh01FFhNOTE:

SFR Information (8)(1)

RegisterSymbolAfter resetThe blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.9

Address0200h0201h0202h0203h0204h0205h0206h0207h0208h0209h020Ah020Bh020Ch020Dh020Eh020Fh0210h0211h0212h0213h0214h0215h0216h0217h0218h0219h021Ah021Bh021Ch021Dh021Eh021Fh0220h0221h0222h0223h0224h0225h0226h0227h0228h0229h022Ah022Bh022Ch022Dh022Eh022Fh0230h0231h0232h0233h0234h0235h0236h0237h0238h0239h023Ah023Bh023Ch023Dh023Eh023FhNOTE:

SFR Information (9)(1)

RegisterSymbolAfter resetThe blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.10

Address0240h0241h0242h0243h0244h0245h0246h0247h0248h0249h024Ah024Bh024Ch024Dh024Eh024Fh0250h0251h0252h0253h0254h0255h0256h0257h0258h0259h025Ah025Bh025Ch025Dh025Eh025Fh0260h0261h0262h0263h0264h0265h0266h0267h0268h0269h026Ah026Bh026Ch026Dh026Eh026Fh0270h0271h0272h0273h0274h0275h0276h0277h0278h0279h027Ah027Bh027Ch027Dh027Eh027FhNOTE:

SFR Information (10)(1)

RegisterSymbolAfter resetThe blank regions are reserved. Do not access locations in these regions.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.11

Address0280h0281h0282h0283h0284h0285h0286h0287h0288h0289h028Ah028Bh028Ch028Dh028Eh028Fh0290h0291h0292h0293h0294h0295h0296h0297h0298h0299h029Ah029Bh029Ch029Dh029Eh029Fh02A0h02A1h02A2h02A3h02A4h02A5h02A6h02A7h02A8h02A9h02AAh02ABh02ACh02ADh02AEh02AFh02B0h02B1h02B2h02B3h02B4h02B5h02B6h02B7h02B8h02B9h02BAh02BBh02BCh02BDh02BEh02BFh

SFR Information (11)(1)

RegisterSymbolAfter resetTimer RF RegisterTRF00h00h

Timer RF Control Register 0Timer RF Control Register 1Capture / Compare 0 RegisterCompare 1 RegisterTRFCR0TRFCR1TRFM0TRFM100h00h0000h(2)FFFFh(3)FFhFFh

NOTES:

1.The blank regions are reserved. Do not access locations in these regions.2.After input capture mode.3.After output compare mode.

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R8C/2C Group, R8C/2D Group

4. Special Function Registers (SFRs)

Table 4.12

Address02C0h02C1h02C2h02C3h02C4h02C5h02C6h02C7h02C8h02C9h02CAh02CBh02CCh02CDh02CEh02CFh02D0h02D1h02D2h02D3h02D4h02D5h02D6h02D7h02D8h02D9h02DAh02DBh02DCh02DDh02DEh02DFh02E0h02E1h02E2h02E3h02E4h02E5h02E6h02E7h02E8h02E9h02EAh02EBh02ECh02EDh02EEh02EFh02F0h02F1h02F2h02F3h02F4h02F5h02F6h02F7h02F8h02F9h02FAh02FBh02FCh02FDh02FEh02FFhFFFFhSFR Information (12)(1)

RegisterA/D Register 0A/D Register 1A/D Register 2A/D Register 3AD0AD1AD2AD3SymbolXXhXXhXXhXXhXXhXXhXXhXXh

After resetA/D Control Register 2A/D Control Register 0A/D Control Register 1ADCON2ADCON0ADCON100001000b00000011b00hPort P7 Direction RegisterPort P7 RegisterPort P8 Direction RegisterPort P9 Direction RegisterPort P8 RegisterPort P9 RegisterPD7P7PD8PD9P8P900hXXh00hX0hXXhXXhPull-Up Control Register 2PUR2XXX00000bTimer RF Output Control RegisterOption Function Select RegisterTRFOUTOFS00h(Note 2)X: UndefinedNOTES:

1.The blank regions are reserved. Do not access locations in these regions.

2.The OFS register cannot be changed by a program. Use a flash programmer to write to it.

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

5.Electrical Characteristics

Table 5.1

SymbolVCC/AVCCVIVOPdToprTstg

Supply voltageInput voltageOutput voltagePower dissipation

Operating ambient temperatureStorage temperature

Topr = 25°C

Absolute Maximum Ratings

Parameter

Condition

Rated Value−0.3 to 6.5−0.3 to VCC + 0.3−0.3 to VCC + 0.3

TBD

−20 to 85 (N version) /−40 to 85 (D version)

−65 to 150

UnitVVVmW°C°C

Table 5.2

SymbolVCC/AVCCVSS/AVSSVIHVILIOH(sum)IOH(sum)IOH(peak)IOH(avg)IOL(sum)IOL(sum)IOL(peak)IOL(avg)f(XIN)

Recommended Operating Conditions

Parameter

Supply voltageSupply voltageInput “H” voltageInput “L” voltagePeak sum output “H” currentAverage sum output “H” currentPeak output “H” currentAverage output “H” currentPeak sum output “L” currentAverage sum output “L” currentPeak output “L” currentAverage output “L” current

Sum of all pins IOH(peak)Sum of all pins IOH(avg)Except P2_0 to P2_7 P2_0 to P2_7Except P2_0 to P2_7 P2_0 to P2_7

Sum of all pins IOL(peak)Sum of all pins IOL(avg)Except P2_0 to P2_7 P2_0 to P2_7Except P2_0 to P2_7 P2_0 to P2_7

3.0 V ≤ VCC ≤ 5.5 V2.7 V ≤ VCC < 3.0 V2.2 V ≤ VCC < 2.7 V

Conditions

Standard

Min.2.2−0.8 VCC

0−−−−−−−−−−−−0000000−

Typ.−0−−−−−−−−−−−−−−−−−−−−−125

Max.5.5−VCC0.2 VCC−240−120−10−40−5−202401201040520201057020105−

UnitVVVVmAmAmAmAmAmAmAmAmAmAmAmAMHzMHzMHzkHzMHzMHzMHzkHz

XIN clock input oscillation frequency

f(XCIN)−

XCIN clock input oscillation frequencySystem clock

OCD2 = 0

XlN clock selectedOCD2 = 1

On-chip oscillator clock selected

2.2 V ≤ VCC ≤ 5.5 V3.0 V ≤ VCC ≤ 5.5 V2.7 V ≤ VCC < 3.0 V2.2 V ≤ VCC < 2.7 VFRA01 = 0

Low-speed on-chip oscillator clock selectedFRA01 = 1

High-speed on-chip oscillator clock selected3.0 V ≤ VCC ≤ 5.5 VFRA01 = 1

High-speed on-chip oscillator clock selected2.7 V ≤ VCC ≤ 5.5 VFRA01 = 1

High-speed on-chip oscillator clock selected2.2 V ≤ VCC ≤ 5.5 V

−−20MHz

−−10MHz

−−5MHz

NOTES:

1.VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.The typical values when average output current is 100 ms.

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

P0P1P2P3P4P5P6P7P8P930pFFigure 5.1Ports P0 to P9 Timing Measurement CircuitTable 5.3

Symbol−−

A/D Converter Characteristics(1)

Parameter

ResolutionAbsolute accuracy

10-bit mode8-bit mode10-bit mode8-bit mode10-bit mode8-bit mode

Vref = AVCC

φAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 3.3 VφAD = 10 MHz, Vref = AVCC = 3.3 VφAD = 5 MHz, Vref = AVCC = 2.2 VφAD = 5 MHz, Vref = AVCC = 2.2 VVref = AVCC

φAD = 10 MHz, Vref = AVCC = 5.0 VφAD = 10 MHz, Vref = AVCC = 5.0 V

8-bit mode

Conditions

StandardMin.−−−−−−−103.32.82.20

Vref = AVCC = 2.7 to 5.5 VVref = AVCC = 2.7 to 5.5 VVref = AVCC = 2.2 to 5.5 VVref = AVCC = 2.2 to 5.5 V

0.2510.251

Without sample and holdWith sample and holdWithout sample and holdWith sample and hold

Typ.−−−−−−−−−−−−−−−−

Max.10±3±2±5±2±5±240−−AVCCAVCC101055

UnitBitLSBLSBLSBLSBLSBLSBkΩµsµsVVMHzMHzMHzMHz

RladdertconvVrefVIA−

Resistor ladder

Conversion time10-bit modeReference voltageAnalog input voltage(2)A/D operating clock frequency

NOTES:

1.VCC/AVCC = Vref = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2.When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

Table 5.4

Symbol−−tsuROIVref

D/A Converter Characteristics(1)

Parameter

ResolutionAbsolute accuracySetup timeOutput resistor

Reference power input current

(NOTE 2)

Conditions

StandardMin.−−−4−

Typ.−−−10−

Max.81.03201.5

UnitBit%µskΩmA

NOTES:

1.VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2.This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.

The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF not connected), IVref flows into the D/A converters.

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.5

Symbol−−−td(SR-SUS)−−−−−−−

Flash Memory (Program ROM) Electrical Characteristics

Parameter

Program/erase endurance(2)Byte program timeBlock erase time

Time delay from suspend request until suspend

Interval from erase start/restart until following suspend request

Interval from program start/restart until following suspend request

Time from suspend until program/erase restart

Program, erase voltageRead voltage

Program, erase temperatureData hold time(7)

Ambient temperature = 55°C

Conditions

R8C/2C GroupR8C/2D Group

Standard

Min.100(3)1,000(3)

−−−6500−2.72.2020

Typ.−−500.4−−−−−−−−

Max.−−400997+CPU clock × 6 cycles

−−3+CPU clock × 4 cycles

5.55.560−

UnittimestimesµssµsµsnsµsVV °Cyear

NOTES:

1.VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.2.Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).3.Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4.In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number.

5.If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6.Customers desiring program/erase failure rate information should contact their Renesas technical support representative.7.The data hold time includes time that the power supply is off or the clock is not supplied.

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.6

Symbol−−−−−td(SR-SUS)−−−−−−−

Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)

Parameter

Program/erase endurance(2)

Byte program time

(program/erase endurance ≤ 1,000 times)Byte program time

(program/erase endurance > 1,000 times)Block erase time

(program/erase endurance ≤ 1,000 times)Block erase time

(program/erase endurance > 1,000 times)Time delay from suspend request until suspend

Interval from erase start/restart until following suspend request

Interval from program start/restart until following suspend request

Time from suspend until program/erase restart

Program, erase voltageRead voltage

Program, erase temperatureData hold time(9)

Ambient temperature = 55 °C

Conditions

Standard

Min.10,000(3)

−−−−−6500−2.72.2−20(8)20

Typ.−50650.20.3−−−−−−−−

Max.−400−9−97+CPU clock × 6 cycles

−−3+CPU clock × 4 cycles

5.55.585−

UnittimesµsµsssµsµsnsµsVV °Cyear

NOTES:

1.VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

4.Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times

is the same as that in program ROM.

5.In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

6.If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

7.Customers desiring program/erase failure rate information should contact their Renesas technical support representative.8.−40°C for D version.

9. The data hold time includes time that the power supply is off or the clock is not supplied.

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Suspend request(maskable interrupt request)FMR46Fixed timeClock-dependenttimeAccess restarttd(SR-SUS)Figure 5.2Time delay until SuspendTable 5.7

SymbolVdet0−td(E-A)Vccmin

Voltage Detection 0 Circuit Electrical Characteristics

Parameter

Voltage detection level

Voltage detection circuit self power consumptionWaiting time until voltage detection circuit operation starts(2)

MCU operating voltage minimum value

VCA25 = 1, VCC = 5.0 V

Condition

StandardMin.2.2−−2.2

Typ.2.30.9−−

Max.2.4−300−

UnitVµAµsV

NOTES:

1.The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2.Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

Table 5.8

SymbolVdet1−−td(E-A)

Voltage Detection 1 Circuit Electrical Characteristics

Parameter

Voltage detection level

Voltage monitor 1 interrupt request generation time(2)Voltage detection circuit self power consumptionWaiting time until voltage detection circuit operation starts(3)

VCA26 = 1, VCC = 5.0 V

Condition

StandardMin.2.70−−−

Typ.2.85400.6−

Max.3.00−−100

UnitVµsµAµs

NOTES:

1.The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).2.Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

3.Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

Table 5.9

SymbolVdet2−−td(E-A)

Voltage Detection 2 Circuit Electrical Characteristics

Parameter

Voltage detection level

Voltage monitor 2 interrupt request generation time(2)Voltage detection circuit self power consumptionWaiting time until voltage detection circuit operation starts(3)

VCA27 = 1, VCC = 5.0 V

Condition

StandardMin.3.3−−−

Typ.3.6400.6−

Max.3.9−−100

UnitVµsµAµs

NOTES:

1.The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).2.Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3.Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

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5. Electrical Characteristics

Table 5.10

SymbolVpor1Vpor2trth

Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)

Parameter

Power-on reset valid voltage(4)

Power-on reset or voltage monitor 0 reset valid voltage

External power VCC rise gradient(2)

Condition

Standard

Min.−020

Typ.−−−

Max.0.1Vdet0−

UnitVVmV/msec

NOTES:

1.The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.

3.To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the

VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.

4.tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on

reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for3,000 s or more if −40°C ≤ Topr < −20°C.

Vdet0(3)2.2VExternalPower VCCVpor1tw(por1)Sampling time(1, 2)trthVpor2trthVdet0(3)Internalreset signal(“L” valid)1fOCO-S× 321fOCO-S× 32NOTES:1.When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltagerange (2.2 V or above) during the sampling time.2.The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.3.Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage DetectionCircuit of Hardware Manual for details.Figure 5.3Power-on Reset Circuit Electrical CharacteristicsRev.1.00Feb 09, 2007REJ03B0183-0100

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5. Electrical Characteristics

Table 5.11

SymbolfOCO40MfOCO40M

High-speed On-Chip Oscillator Circuit Electrical Characteristics

Parameter

High-speed on-chip oscillator frequency after reset

High-speed on-chip oscillator temperature supply voltage dependence

Condition

VCC = 5.0 V, Topr = 25°CVCC = 2.7 V to 5.5 V−20°C ≤ Topr ≤ 85°C(2)VCC = 2.7 V to 5.5 V−40°C ≤ Topr ≤ 85°C(2)VCC = 2.2 V to 5.5 V−20°C ≤ Topr ≤ 85°C(3)VCC = 2.2 V to 5.5 V−40°C ≤ Topr ≤ 85°C(3)

Standard

Min.−39.239.035.234.008h

Adjust FRA1 register (value after reset) to −1VCC = 5.0 V, Topr = 25°CVCC = 5.0 V, Topr = 25°C

−−−

Typ.40−−−−−+0.310550

Max.−40.841.044.846.0F7h−100−

UnitMHzMHzMHzMHzMHz−MHzµsµA

−−−−

Value in FRA1 register after reset

Oscillation frequency adjustment unit of high-speed on-chip oscillator Oscillation stability time

Self power consumption at oscillation

NOTES:

1.VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.These standard values show when the FRA1 register value after reset is assumed.

3.These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.

Table 5.12

SymbolfOCO-S−−

Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Parameter

Low-speed on-chip oscillator frequencyOscillation stability time

Self power consumption at oscillation

VCC = 5.0 V, Topr = 25°CVCC = 5.0 V, Topr = 25°C

Condition

Standard

Min.30−−

Typ.1251015

Max.250100−

UnitkHzµsµA

NOTE:

1.VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Table 5.13

Symboltd(P-R)td(R-S)

Power Supply Circuit Timing Characteristics

Parameter

Time for internal power supply stabilization during power-on(2)STOP exit time(3)

Condition

StandardMin.1−

Typ.−−

Max.2000150

Unitµsµs

NOTES:

1.The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.

2.Waiting time until the internal power supply generation circuit stabilizes during power-on.3.Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.

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5. Electrical Characteristics

Table 5.14

SymboltSUCYCtHItLOtRISEtFALLtSUtHtLEADtLAGtODtSAtOR

Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)

Parameter

SSCK clock cycle timeSSCK clock “H” widthSSCK clock “L” widthSSCK clock rising time

SSCK clock falling time

MasterSlaveMasterSlave

Conditions

Standard

Min.40.40.4−−−−10011tCYC + 501tCYC + 50

−

2.7 V ≤ VCC ≤ 5.5 V2.2 V ≤ VCC < 2.7 V

SSI slave out open time

2.7 V ≤ VCC ≤ 5.5 V2.2 V ≤ VCC < 2.7 V

−−−−

Typ.−−−−−−−−−−−−−−−−

Max.−0.60.61111−−−−11.5tCYC + 1001.5tCYC + 2001.5tCYC + 1001.5tCYC + 200

UnittCYC(2)tSUCYCtSUCYCtCYC(2)µstCYC(2)µsnstCYC(2)nsnstCYC(2)nsnsnsns

SSO, SSI data input setup timeSSO, SSI data input hold timeSCS setup timeSCS hold timeSSI slave access time

SlaveSlave

SSO, SSI data output delay time

NOTES:

1.VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.1tCYC = 1/f1(s)

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5. Electrical Characteristics

4-Wire Bus Communication Mode, Master, CPHS = 1SCS (output)VIH or VOHVIH or VOHtHItFALLtRISESSCK (output)(CPOS = 1)tLOtHISSCK (output)(CPOS = 0)tLOtSUCYCSSO (output)tODSSI (input)tSUtH4-Wire Bus Communication Mode, Master, CPHS = 0SCS (output)VIH or VOHVIH or VOHtHItFALLtRISESSCK (output)(CPOS = 1)tLOtHISSCK (output)(CPOS = 0)tLOtSUCYCSSO (output)tODSSI (input)tSUtHCPHS, CPOS: Bits in SSMR registerFigure 5.4I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

4-Wire Bus Communication Mode, Slave, CPHS = 1VIH or VOHSCS (input)VIH or VOHtLEADtHItFALLtRISEtLAGSSCK (input)(CPOS = 1)tLOtHISSCK (input)(CPOS = 0)tLOtSUCYCSSO (input)tSUtHSSI (output)tSAtODtOR4-Wire Bus Communication Mode, Slave, CPHS = 0SCS (input)VIH or VOHVIH or VOHtLEADtHItFALLtRISEtLAGSSCK (input)(CPOS = 1)tLOtHISSCK (input)(CPOS = 0)tLOtSUCYCSSO (input)tSUtHSSI (output)tSAtODtORCPHS, CPOS: Bits in SSMR registerFigure 5.5I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)Rev.1.00Feb 09, 2007REJ03B0183-0100

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5. Electrical Characteristics

tHIVIH or VOHSSCKVIH or VOHtLOtSUCYCSSO (output)tODSSI (input)tSUtHFigure 5.6I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.15

SymboltSCLtSCLHtSCLLtsftSPtBUFtSTAHtSTAStSTOPtSDAStSDAH

Timing Requirements of I2C bus Interface (1)

Parameter

SCL input cycle timeSCL input “H” widthSCL input “L” width

SCL, SDA input fall time

SCL, SDA input spike pulse rejection timeSDA input bus-free timeStart condition input hold time

Retransmit start condition input setup timeStop condition input setup timeData input setup timeData input hold time

Condition

Standard

Min.Typ.

−12tCYC + 600(2)

−3tCYC + 300(2)5tCYC + 500(2)

−−5tCYC(2)3tCYC(2)3tCYC(2)3tCYC(2)1tCYC + 20(2)

−−−−−−−−−

Max.−

−−

Unitnsnsnsnsnsnsnsnsnsnsns

3001tCYC(2)

−

−−−−−

NOTES:

1.VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.2.1tCYC = 1/f1(s)

SDAtBUFVIHVILtSTAHtSCLHtSPtSTOPtSTASSCLP(2)S(1)tsftSCLLtSCLNOTES: 1. Start condition 2. Stop condition 3. Retransmit start conditionSr(3)tsrtSDAHtSDASP(2)Figure 5.7I/O Timing of I2C bus InterfaceRev.1.00Feb 09, 2007REJ03B0183-0100

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5. Electrical Characteristics

Table 5.16

SymbolVOH

Electrical Characteristics (1) [VCC = 5 V]

Parameter

Condition

Standard

Min.Typ.VCC − 2.0−VCC − 0.5−VCC − 2.0−VCC − 2.0−VCC − 2.0−VCC − 2.0−

−−−−−−−−−−−−0.10.5

Max.

VCCVCCVCCVCCVCCVCC2.00.452.02.02.02.0−

UnitVVVVVVVVVVVVV

VOL

VT+-VT-

Output “H” voltageExcept P2_0 to P2_7, IOH = −5 mA

XOUTIOH = −200 µAP2_0 to P2_7Drive capacity HIGH

Drive capacity LOW

XOUTDrive capacity HIGH

Drive capacity LOW

Output “L” voltageExcept P2_0 to P2_7, IOL = 5 mA

XOUTIOL = 200 µAP2_0 to P2_7Drive capacity HIGH

Drive capacity LOW

XOUTDrive capacity HIGH

Drive capacity LOW

HysteresisINT0, INT1, INT2,

INT3, KI0, KI1, KI2, KI3, TRAIO, TRFI, RXD0, RXD1, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSO

RESET

Input “H” currentInput “L” currentPull-up resistanceFeedback XINresistanceFeedback XCINresistance

RAM hold voltage

VI = 5 VVI = 0 VVI = 0 V

IOH = −20 mAIOH = −5 mAIOH = −1 mAIOH = −500 µA

IOL = 20 mAIOL = 5 mAIOL = 1 mAIOL = 500 µA

0.1

−−

1.0

−−

−V

µAµA

IIHIIL

RPULLUPRfXINRfXCINVRAM

30−

−

501.018

−

5.0−5.0167−

−−

kΩMΩMΩV

During stop mode1.8

NOTE:

1.VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.

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5. Electrical Characteristics

Table 5.17

SymbolICC

Electrical Characteristics (2) [Vcc = 5 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Parameter

Condition

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 16 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 20 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 16 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8XIN clock offHigh-speed on-chip oscillator on fOCO = 10 MHzLow-speed on-chip oscillator on = 125 kHzNo divisionXIN clock offHigh-speed on-chip oscillator on fOCO = 10 MHzLow-speed on-chip oscillator on = 125 kHzDivide-by-8XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8, FMR47 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz FMR47 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz Program operation on RAMFlash memory off, FMSTP = 1XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock operationVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock off

VCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1

XIN clock off, Topr = 25°CHigh-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0XIN clock off, Topr = 85°CHigh-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

Power supply High-speed current clock mode(VCC = 3.3 to 5.5 V)Single-chip mode, output pins are open, other pins are VSS

StandardMin.Typ.Max.−1220UnitmA−1016mA−7−mA−5.5−mA−4.5−mA−3−mAHigh-speed on-chip

oscillator mode

−612mA−2.5−mALow-speed on-chip

oscillator modeLow-speed clock mode

−150400µA−150400µA−35−µAWait mode−3090µA−1855µA−3.5−µA−2.3−µAStop mode−0.73.0µA−1.7−µARev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

Timing Requirements

(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]Table 5.18

Symboltc(XIN)tWH(XIN)tWL(XIN)tc(XCIN)tWH(XCIN)tWL(XCIN)

XIN input cycle timeXIN input “H” widthXIN input “L” widthXCIN input cycle timeXCIN input “H” widthXCIN input “L” width

5. Electrical Characteristics

XIN Input, XCIN Input

Parameter

StandardMin.Max.50−25−25−14−7−7−

Unitns

nsnsµsµsµs

tC(XIN)tWH(XIN)VCC = 5 VXIN inputtWL(XIN)Figure 5.8Table 5.19

Symboltc(TRAIO)tWH(TRAIO)tWL(TRAIO)

XIN Input and XCIN Input Timing Diagram when VCC = 5 VTRAIO Input, INT1 Input

Parameter

TRAIO input cycle timeTRAIO input “H” widthTRAIO input “L” width

StandardMin.Max.100−40−40−

Unitns

nsns

tC(TRAIO)tWH(TRAIO)VCC = 5 VTRAIO inputtWL(TRAIO)Figure 5.9Table 5.20

Symboltc(TRFI)tWH(TRFI)tWL(TRFI)

TRAIO Input and INT1 Input Timing Diagram when VCC = 5 VTRFI Input

Parameter

TRFI input cycle timeTRFI input “H” widthTRFI input “L” width

StandardMin.Max.

−400(1)200(2)200(2)

−−

Unitnsnsns

NOTES:

1.When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.2.When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.

tc(TRFI)tWH(TRFI)TRFI inputtWL(TRFI)VCC = 5 VFigure 5.10TRFI Input Timing Diagram when VCC = 5 VPage 45 of 55

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.21

Symboltc(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)i = 0 to 2

Serial Interface

Parameter

CLKi input cycle timeCLKi input “H” widthCLKi input “L” widthTXDi output delay timeTXDi hold time

RXDi input setup timeRXDi input hold time

StandardMin.Max.200−100−100−−500−50−90−

Unitns

nsnsnsnsnsns

tC(CK)tW(CKH)VCC = 5 VCLKitW(CKL)th(C-Q)TXDitd(C-Q)tsu(D-C)th(C-D)RXDii = 0 to 2Figure 5.11Serial Interface Timing Diagram when VCC = 5 VTable 5.22

SymboltW(INH)tW(INL)

External Interrupt INTi (i = 0, 2, 3) Input

Parameter

INT0 input “H” widthINT0 input “L” width

StandardMin.Max.

−250(1)250(2)

−

Unitnsns

NOTES:

1.When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2.When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 5 VtW(INL)INTi inputi = 0, 2, 3tW(INH)Figure 5.12External Interrupt INTi Input Timing Diagram when VCC = 5 VRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.23

SymbolVOH

Electrical Characteristics (3) [VCC = 3 V]

Parameter

Condition

Standard

Min.Typ.VCC − 0.5−VCC − 0.5VCC − 0.5VCC − 0.5VCC − 0.5

−

−−−−−−−−−

Output “H” voltage

VOLOutput “L” voltage

Except P2_0 to P2_7, IOH = −1 mA

XOUT

P2_0 to P2_7Drive capacity

HIGH

Drive capacity LOW

XOUTDrive capacity

HIGH

Drive capacity LOW

Except P2_0 to P2_7, IOL = 1 mAXOUT

P2_0 to P2_7Drive capacity

HIGH

Drive capacity LOW

XOUTDrive capacity

HIGH

Drive capacity LOWINT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRFI, RXD0, RXD1, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSORESET

VI = 3 VVI = 0 VVI = 0 V

XINXCIN

During stop mode

Max.VCCVCCVCCVCCVCC0.50.50.50.50.5

−

UnitVVVVVVVVVVV

IOH = −5 mAIOH = −1 mAIOH = −0.1 mAIOH = −50 µA

IOL = 5 mAIOL = 1 mAIOL = 0.1 mAIOL = 50 µA

−−−−

VT+-VT-Hysteresis0.10.3

0.1

−−

0.4

−−

−V

µAµA

IIHIIL

RPULLUPRfXINRfXCINVRAMInput “H” currentInput “L” currentPull-up resistanceFeedback resistanceFeedback resistanceRAM hold voltage

66−−1.81603.018−

4.0−4.0500−−−

kΩMΩMΩV

NOTE:

1.VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.24

SymbolICC

Electrical Characteristics (4) [Vcc = 3 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Parameter

Condition

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 10 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8XIN clock off

High-speed on-chip oscillator on fOCO = 10 MHzLow-speed on-chip oscillator on = 125 kHzNo divisionXIN clock offHigh-speed on-chip oscillator on fOCO = 10 MHzLow-speed on-chip oscillator on = 125 kHzDivide-by-8XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8, FMR47 = 1

XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz FMR47 = 1XIN clock off

High-speed on-chip oscillator offLow-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz Program operation on RAMFlash memory off, FMSTP = 1XIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock operationVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock off

VCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock off

High-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1

XIN clock off, Topr = 25°C

High-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0XIN clock off, Topr = 85°C

High-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

StandardMin.Typ.Max.−5.5−

UnitmA

Power supply current High-speed

(VCC = 2.7 to 3.3 V)clock modeSingle-chip mode, output pins are open, other pins are VSS

−2−mAHigh-speed on-chip oscillator mode

−5.511mA

−2.2−mALow-speed on-chip oscillator mode

Low-speed clock mode

−145400µA

−145400µA−30−µA

Wait mode−2885µA−1750µA

−3.3−µA−2.1−µA

Stop mode−0.653.0µA−1.65−µA

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

Timing requirements

(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]Table 5.25

Symboltc(XIN)tWH(XIN)tWL(XIN)tc(XCIN)tWH(XCIN)tWL(XCIN)

XIN input cycle timeXIN input “H” widthXIN input “L” widthXCIN input cycle timeXCIN input “H” widthXCIN input “L” width

5. Electrical Characteristics

XIN Input, XCIN Input

Parameter

StandardMin.Max.100−40−40−14−7−7−

Unitns

nsnsµsµsµs

tC(XIN)tWH(XIN)VCC = 3 VXIN inputtWL(XIN)Figure 5.13Table 5.26

Symboltc(TRAIO)tWH(TRAIO)tWL(TRAIO)

XIN Input and XCIN Input Timing Diagram when VCC = 3 VTRAIO Input, INT1 Input

Parameter

TRAIO input cycle timeTRAIO input “H” widthTRAIO input “L” width

StandardMin.Max.300−120−120−

Unitns

nsns

tC(TRAIO)tWH(TRAIO)VCC = 3 VTRAIO inputtWL(TRAIO)Figure 5.14Table 5.27

Symboltc(TRFI)tWH(TRFI)tWL(TRFI)

TRAIO Input and INT1 Input Timing Diagram when VCC = 3 VTRFI Input

Parameter

TRFI input cycle timeTRFI input “H” widthTRFI input “L” width

StandardMin.Max.

−1200(1)600(2)600(2)

−−

Unitnsnsns

NOTES:

tc(TRFI)tWH(TRFI)TRFI inputtWL(TRFI)VCC = 3 VFigure 5.15TRFI Input Timing Diagram when VCC = 3 VRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.28

Symboltc(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)i = 0 to 2

Serial Interface

Parameter

CLKi input cycle timeCLKi input “H” widthCLKi Input “L” widthTXDi output delay timeTXDi hold time

RXDi input setup timeRXDi input hold time

StandardMin.Max.300−150−150−−800−70−90−

Unitns

nsnsnsnsnsns

tC(CK)tW(CKH)VCC = 3 VCLKitW(CKL)th(C-Q)TXDitd(C-Q)tsu(D-C)th(C-D)RXDii = 0 to 2Figure 5.16Serial Interface Timing Diagram when VCC = 3 VTable 5.29

SymboltW(INH)tW(INL)

External Interrupt INTi (i = 0, 2, 3) Input

Parameter

INT0 input “H” widthINT0 input “L” widthStandardMin.Max.

−380(1)380(2)

−

Unitnsns

NOTES:

1.When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2.When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 3 VtW(INL)INTi inputtW(INH)i = 0, 2, 3Figure 5.17External Interrupt INTi Input Timing Diagram when VCC = 3 VRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.30

SymbolVOH

Electrical Characteristics (5) [VCC = 2.2 V]

Parameter

Condition

Standard

Min.Typ.VCC − 0.5−VCC − 0.5VCC − 0.5VCC − 0.5VCC − 0.5

−

−−−−−−−−−

Output “H” voltage

VOLOutput “L” voltage

Except P2_0 to P2_7, IOH = −1 mA

XOUT

P2_0 to P2_7Drive capacity

HIGH

Drive capacity LOW

XOUTDrive capacity

HIGH

Drive capacity LOW

Except P2_0 to P2_7, IOL = 1 mAXOUT

P2_0 to P2_7Drive capacity

HIGH

Drive capacity LOW

XOUTDrive capacity

HIGH

Drive capacity LOWINT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRFI, RXD0, RXD1, CLK0, CLK1, CLK2, SSI, SCL, SDA, SSORESET

VI = 2.2 VVI = 0 VVI = 0 V

XINXCIN

During stop mode

Max.VCCVCCVCCVCCVCC0.50.50.50.50.5

−

UnitVVVVVVVVVVV

IOH = −2 mAIOH = −1 mAIOH = −0.1 mAIOH = −50 µA

IOL = 2 mAIOL = 1 mAIOL = 0.1 mAIOL = 50 µA

−−−−

VT+-VT-Hysteresis0.050.3

0.05

−−

0.15

−−

−V

µAµA

IIHIIL

RPULLUPRfXINRfXCINVRAMInput “H” currentInput “L” currentPull-up resistanceFeedback resistanceFeedback resistanceRAM hold voltage

100−−1.8200535−

4.0−4.0600−−−

kΩMΩMΩV

NOTE:

1.VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.31

SymbolICC

Electrical Characteristics (6) [Vcc = 2.2 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Parameter

Condition

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzNo division

XIN = 5 MHz (square wave)High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzDivide-by-8

High-speed XIN clock off

High-speed on-chip oscillator on fOCO = 5 MHzon-chip

Low-speed on-chip oscillator on = 125 kHz

oscillator No divisionmode

XIN clock offHigh-speed on-chip oscillator on fOCO = 5 MHzLow-speed on-chip oscillator on = 125 kHzDivide-by-8

Low-speed on-XIN clock off

chip oscillator High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzmode

Divide-by-8, FMR47 = 1

Low-speed XIN clock offHigh-speed on-chip oscillator offclock mode

Low-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz FMR47 = 1XIN clock off

High-speed on-chip oscillator offLow-speed on-chip oscillator offXCIN clock oscillator on = 32 kHz Program operation on RAMFlash memory off, FMSTP = 1

Wait modeXIN clock offHigh-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock operationVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHzWhile a WAIT instruction is executedPeripheral clock off

VCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (high drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1XIN clock off

High-speed on-chip oscillator offLow-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (low drive)While a WAIT instruction is executedVCA27 = VCA26 = VCA25 = 0VCA20 = 1

Stop modeXIN clock off, Topr = 25°C

High-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0XIN clock off, Topr = 85°C

High-speed on-chip oscillator offLow-speed on-chip oscillator offCM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

StandardMin.Typ.Max.−2.5−

UnitmA

Power supply current High-speed

(VCC = 2.2 to 2.7 V)clock modeSingle-chip mode, output pins are open, other pins are VSS

−1−mA−4−mA

−1.7−mA−110300µA

−125350µA−27−µA

−2060µA−1240µA

−2.8−µA−1.9−µA

−0.63.0µA−1.60−µA

Rev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Timing requirements

(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]Table 5.32

Symboltc(XIN)tWH(XIN)tWL(XIN)tc(XCIN)tWH(XCIN)tWL(XCIN)

XIN input cycle timeXIN input “H” widthXIN input “L” widthXCIN input cycle timeXCIN input “H” widthXCIN input “L” width

XIN Input, XCIN Input

Parameter

StandardMin.Max.200−90−90−14−7−7−

Unitns

nsnsµsµsµs

tC(XIN)tWH(XIN)VCC = 2.2 VXIN inputtWL(XIN)Figure 5.18Table 5.33

Symboltc(TRAIO)tWH(TRAIO)tWL(TRAIO)

XIN Input and XCIN Input Timing Diagram when VCC = 2.2 VTRAIO Input, INT1 Input

Parameter

TRAIO input cycle timeTRAIO input “H” widthTRAIO input “L” width

StandardMin.Max.TBD−TBD−TBD−

Unitns

nsns

tC(TRAIO)tWH(TRAIO)VCC = 2.2 VTRAIO inputtWL(TRAIO)Figure 5.19Table 5.34

Symboltc(TRFI)tWH(TRFI)tWL(TRFI)

TRAIO Input and INT1 Input Timing Diagram when VCC = 2.2 VTRFI Input

Parameter

TRFI input cycle timeTRFI input “H” widthTRFI input “L” width

StandardMin.Max.

−2000(1)1000(2)1000(2)

−−

Unitnsnsns

NOTES:

tc(TRFI)tWH(TRFI)TRFI inputtWL(TRFI)VCC = 2.2 VFigure 5.20TRFI Input Timing Diagram when VCC = 2.2 VRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

5. Electrical Characteristics

Table 5.35

Symboltc(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)i = 0 to 2

Serial Interface

Parameter

CLKi input cycle timeCLKi input “H” widthCLKi input “L” widthTXDi output delay timeTXDi hold time

RXDi input setup timeRXDi input hold time

StandardMin.Max.800−400−400−−2000−150−90−

Unitns

nsnsnsnsnsns

tC(CK)tW(CKH)VCC = 2.2 VCLKitW(CKL)th(C-Q)TXDitd(C-Q)tsu(D-C)th(C-D)RXDii = 0 to 2Figure 5.21Serial Interface Timing Diagram when VCC = 2.2 VTable 5.36

SymboltW(INH)tW(INL)

External Interrupt INTi (i = 0, 2, 3) Input

Parameter

INT0 input “H” widthINT0 input “L” widthStandardMin.Max.

−1000(1)1000(2)

−

Unitnsns

NOTES:

1.When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2.When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

VCC = 2.2 VtW(INL)INTi inputi = 0, 2, 3tW(INH)Figure 5.22External Interrupt INTi Input Timing Diagram when VCC = 2.2 VRev.1.00Feb 09, 2007REJ03B0183-0100

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R8C/2C Group, R8C/2D Group

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section ofthe Renesas Technology website.

JEITA Package CodeP-LQFP80-12x12-0.50RENESAS CodePLQP0080KB-APrevious Code80P6Q-AMASS[Typ.]0.5gHD*1D41NOTE)1.DIMENSIONS \"*1\" AND \"*2\"DO NOT INCLUDE MOLD FLASH.2.DIMENSION \"*3\" DOES NOTINCLUDE TRIM OFFSET.606140bpb1c1*2HEEcReferenceSymbolDimension in MillimetersTerminal cross section80211ZDIndex mark20FDEA2HDHEAA1bpb1cc1exyZDZELL1yeA1*3bpxLL1Detail FMinNomMax11.912.012.111.912.012.11.413.814.014.213.814.014.21.70.10.200.150.200.250.180.090.1450.200.1250°10°0.50.080.081.251.250.30.50.71.0ZEA2ARev.1.00Feb 09, 2007REJ03B0183-0100

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REVISION HISTORYREVISION HISTORY

Rev.0.010.10

DateApr 03, 2006Jun 26, 2006

R8C/2C Group, R8C/2D Group DatasheetR8C/2C Group, R8C/2D Group Datasheet

Description

Page

−

Summary

First Edition issued

All pagesPin name revised

CMP0_0 → TRFO00, CMP0_1 → TRFO01, CMP0_2 → TRFO02, CMP1_0 → TRFO10, CMP1_1 → TRFO11, CMP1_2 → TRFO12, TRFIN → TRFI2, 4

Table 1.1 Specifications for R8C/2C Group (1) and Table 1.3 Specifications for R8C/2D Group (1);

I/O Ports: • Input-only: 3 pins → 2 pins revised

Interrupts: • Internal: 17 sources → 23 sources revisedTable 1.2 Specifications for R8C/2C Group (2) and Table 1.4 Specifications for R8C/2D Group (2);ROM Correction Function deletedFigure 1.3 Block Diagram revised

Figure 1.4 Pin Assignment (Top View) revised

Table 1.7 Pin Name Information by Pin Number (1) and Table 1.8 Pin Name Information by Pin Number (2) revised

Table 1.9 Pin Functions (1) and Table 1.10 Pin Functions (2) revisedTable 4.1 SFR Information (1);

•0008h: Module Standby Control Register, MSTCR, 00h added•001Ch: “00h” → “00h, 10000000b” revised•NOTE6 added

Table 4.2 SFR Information (2);

•005Fh: Capture Interrupt Control Register, CAPIC, XXXXX000b addedTable 4.4 SFR Information (4);

•00DCh: “00DDh” → “00DCh” revised•00F5h: “XXXX00XXb” → “00h” revised

Table 4.5 SFR Information (5);

•0105h: LIN Special Function Register, LINCR2, 00h addedPackage Dimensions;

“Diagrams showing the latest package dimensions ... in the “Packages” section of the Renesas Technology website.” addedTable 1.5 and Figure 1.1 revisedTable 1.6 and Figure 1.2 revisedFigure 3.1 revisedFigure 3.2 revised

Table 4.1;

•000Ah: “00XXX000b” → “00h” revised

•0008h: “Module Standby Control Register” → “Module Operation Enable Register” revised•000Fh: “00011111b” → “00X11111b” revisedTable 5.11 revised

3, 5

8910, 1112, 1319

2022

2331

0.200.30

Sep 15, 2006Dec 22, 2006

31 to 545. Electrical Characteristics added

67171819

A - 1

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REVISION HISTORY

Rev.1.00

DateFeb 09, 2007

R8C/2C Group, R8C/2D Group Datasheet

Description

Page

All pages“Preliminary” deleted

3567171819

Table 1.2 revisedTable 1.4 revised

Summary

Table 1.5 and Figure 1.1 revisedTable 1.6 and Figure 1.2 revisedFigure 3.1 revisedFigure 3.2 revised

Table 4.1;

•0008h: “Module Standby Control Register” → “Module Operation Enable Register” revised•000Ah: “00XXX000b” → “00h” revised

•000Fh: “00011111b” → “00X11111b” revised

•002Bh: “High-Speed On-Chip Oscillator Control Register 6” addedTable 4.5;

0105h: “LIN Control Register 2” register name revisedTable 5.2 revised

Table 5.3 and Table 5.4; NOTE1 revisedTable 5.11 revisedTable 5.17 revised

Table 5.21 and Figure 5.11; “i = 0 to 2” revisedTable 5.24 revised

Table 5.28 revised, Figure 5.16; “i = 0 to 2” revisedTable 5.31 revisedTable 5.34 revised

Table 5.35 and Figure 5.21; “i = 0 to 2” revised

2331323744464850525354

A - 2

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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanNotes:1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.3. 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