Low power logic output buffer

专利名称：Low power logic output buffer发明人：Brian J. Buell申请号：US11557320申请日：20061107公开号：US07564268B2公开日：20090721

专利附图：

摘要：A low power logic output buffer includes first and second logic gates, eachhaving an input and an output. The input of the first logic gate receives a first logic signal,and the input of the second logic gate receives a second logic signal. The buffer includesfirst, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also

includes first and second bias switching NMOS. The first bias switching NMOS is coupledbetween the source of the third NMOS and ground, and the gate of the first biasswitching NMOS is coupled to the output of the first logic gate. The second biasswitching NMOS is electrically coupled between the source of the fourth NMOS andground, and the gate of the second bias switching NMOS is coupled to the output of thesecond logic gate.

申请人：Brian J. Buell

地址：Gilbert AZ US

国籍：US

代理机构：Panitch, Schwarze, et al.

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