LM3880 Power SequencerMarch 2007
LM3880
Power Sequencer
General Description
The LM3880 Power Sequencer offers the easiest method tocontrol power up and power down of multiple power supplies(switchers or linear regulators). By staggering the startup se-quence, it is possible to avoid latch conditions or large in-rushcurrents that can affect the reliability of the system.
Available in a SOT23-6 package, the Power Sequencer con-tains a precision enable pin and three open drain output flags.Upon enabling the LM3880 the three output flags will sequen-tially release, after individual time delays, permitting the con-nected power supplies to startup. The output flags will followa reverse sequence during power down to avoid latch condi-tions.
Standard timing option of 30ms is available.
EPROM capability allows every delay and sequence to befully adjustable. Contact National Semiconductor if a non-standard configuration is required.
Features
■■■■■■■
Easiest method to sequence railsPower up and power down controlInput voltage range of 2.7V to 5.5VSmall footprint SOT23-6
Low quiescent current of 25 µAStandard timing options available
Customization of timing and sequence available throughfactory programmability
Applications
■Multiple supply sequencing
■Microprocessor / Microcontroller sequencing■FPGA sequencing
Typical Application Circuit
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LM3880Connection Diagram
Top View
SOT23–6 Package
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Pin Descriptions
Pin #123456
NameVCCGNDENFLAG3FLAG2FLAG1
FunctionInput supplyGroundPrecision enable pinOpen drain output #3Open drain output #2Open drain output #1
Ordering Information
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Sequence Designator Table
Sequence Number
Power Up
123456
See timing diagrams for more information
Flag Order
Power Down3 - 2 - 13 - 1 - 22 - 3 - 12 - 1 - 31 - 3 - 21 - 2 - 3
1 - 2 - 31 - 2 - 31 - 2 - 31 - 2 - 31 - 2 - 31 - 2 - 3
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LM3880Timing Designator Table
TimingDesignator
AAABACAD
td110ms30ms60ms120ms
td210ms30ms60ms120ms
td310ms30ms60ms120ms
td410ms30ms60ms120ms
td510ms30ms60ms120ms
td610ms30ms60ms120ms
See timing diagrams for more information
LM3880 Ordering Information
OrderNumberLM3880MF-1AALM3880MFX-1AALM3880MF-1ABLM3880MFX-1ABLM3880MF-1ACLM3880MFX-1ACLM3880MF-1ADLM3880MFX-1AD
Timer settings
td110ms10ms30ms30ms60ms60ms120ms120ms
td210ms10ms30ms30ms60ms60ms120ms120ms
td310ms10ms30ms30ms60ms60ms120ms120ms
td410ms10ms30ms30ms60ms60ms120ms120ms
td510ms10ms30ms30ms60ms60ms120ms120ms
td610ms10ms30ms30ms60ms60ms120ms120ms
SequenceOrderSupplied As
Package
Type
NSCPackageDrawing
PackageMarkingF20AF20AF21AF21A
SOT23-6
1111
1k units T&R3k units T&R1k units T&R3k units T&R
MF06A
F22AF22AF23AF23A
1111
1k units T&R3k units T&R1k units T&R3k units T&R
Non-standard parts are available upon request. Please contact National Semiconductor for more information.
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LM3880Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.VCC
EN, FLAG1, FLAG2, FLAG3Max Flag 'ON' Current
Storage Temperature RangeJunction Temperature
Lead Temperature (Soldering, 5sec.)
Minimum ESD Rating
−0.3V to +6.0V−0.3V to 6.0V
50 mA
−65°C to +150°C
150°C
260°C±2 kV
Operating Ratings
VCC to GND
EN, FLAG1, FLAG2, FLAG3Junction Temperature
(Note 1)
2.7V to 5.5V
−0.3V to VCC + 0.3V−40°C to +125°C
Specifications with standard typeface are for TJ = 25°C, and those in bold face type
apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Minimum and Maximum limits are guaranteed throughtest, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided forreference purposes only. Unless otherwise specified VCC = 3.3V.
SymbolIQ
Open Drain Flags
IFLAGVOL
Power Up Sequence
td1td2td3td4td5td6
Timing Delay Error
(td(x) – 400 us) / td(x+1)Ratio of timing delays
td(x) / td(x+1)
ENABLE Pin
VENIEN
EN pin thresholdEN pin pull-up current
VEN = 0V
1.0
1.257
1.4
VµA
Ratio of timing delays
For x = 1 or 4For x = 2 or 5
9595
105105
%%
Timer delay 1 accuracyTimer delay 2 accuracyTimer delay 3 accuracyTimer delay 4 accuracyTimer delay 5 accuracyTimer delay 6 accuracy
-15-15-15-15-15-15
_
151515151515
%%%%%%
FLAGx Leakage CurrentFLAGx Output Voltage Low
VFLAGx = 3.3VIFLAGx = 1.2mA
1
200.4
nAV
Parameter
Operating Quiescent current
Conditions
Min(Note 3)
Typ(Note 4)25
Max(Note 3)80
UnitµA
Electrical Characteristics
Power Down Sequence
Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isintended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.Note 2:The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3:Limits are 100% production tested at 25°. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control(SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).Note 4:Typical numbers are at 25°C and represent the most likely parametric norm.
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LM3880Typical Performance Characteristics
Quiescent Current vs VCC
Quiescent Current vs Temperature (VCC = 3.3V)
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20192604
Enable Threshold vs TemperatureTime Delay (30ms) vs VCC
2019260620192607
Time Delay Ratio vs TemperatureTime Delay (30ms) vs Temperature
2019260820192609
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LM3880FLAG VOL vs VCC(RFLAG = 100 kΩ)
FLAG Voltage vs Current
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Block Diagram
Block Diagram
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LM3880Timing Diagrams (Sequence 1)
All standard options use this sequence for output flags rise and fall order.
Power Up Sequence
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Power Down Sequence
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Application Information
OVERVIEW
The LM3880 Power Sequencer provides an easy solution forsequencing multiple rails in a controlled manner. Six inde-pendent timers are integrated to control the timing sequence(power up and power down) of three open drain output flags.These flags permit connection to either a shutdown / enablepin of linear regulators and switchers to control the powersupplies’ operation. This allows a complete power system tobe designed without worrying about large in-rush currents orlatch-up conditions that can occur.
The timing sequence of the LM3880 is controlled entirely bythe enable (EN) pin. Upon power up, all the flags are held lowuntil this precision enable is pulled high. After the EN pin isasserted, the power up sequence will commence. An internalcounter will delay the first flag (FLAG1) from rising until a fixedtime period has expired. Upon the release of the first flag an-other timer will begin to delay the release of the second flag(FLAG2). This process repeats until all three flags have se-quentially been released. The three timers that control thedelays are all independent of each other and can be individ-ually programmed if needed. (See custom sequencer sec-tion).
The power down sequence is the same as power-up, but inreverse. When EN pin is de-asserted a timer will begin thatdelays the third flag (FLAG3) from pulling low. The secondand first flag will then follow in a sequential manner after their
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appropriate delays. The three timers that are used to controlthe power down scheme can also be individually programmedand are completely independent of the power up timers.Additional sequence patterns are also available in addition tocustomizable timers. For more information see the customsequencer section.
PART OPERATION
The timing sequence of the LM3880 is controlled by the as-sertion of the enable signal. The enable pin is designed withan internal comparator, referenced to a bandgap voltage(1.25V), to provide a precision threshold. This allows a de-layed timing to be externally set using a capacitor or to startthe sequencing based on a certain event, such as a line volt-age reaching 90% of nominal. For an additional delayedsequence from the rail powering VCC, simply attach a ca-pacitor to the EN pin as shown below.
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LM3880Cap Timing
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Using the internal pull-up current source to charge the exter-nal capacitor (CEN) the enable pin delay can be calculated bythe equation below:
A resistor divider can also be used to enable the LM3880based on a certain voltage threshold. Care needs to be takenwhen sizing the resistor divider to include the effects of theinternal current source.
One of the features of the enable pin is that it provides glitchfree operation. The first timer will start counting at a risingthreshold, but will always reset if the enable pin is de-assertedbefore the first output flag is released. This can be shown inthe timing diagram below:
EN Glitch
If the enable signal remains high for the entire power-up se-When this event occurs, the falling edge of enable pin resets
quence, then the part will operate as shown in the standardthe current timer and will allow the remaining power-up cycletiming diagrams. However, if the enable signal is de-assertedto complete before beginning the power down sequence. Thebefore the power-up sequence is completed the part will enterpower down sequence starts approximately 120ms after thea controlled shutdown. This allows the system to walk throughfinal power-up flag. This allows output voltages in the systema controlled power cycling, preventing any latch conditionsto stabilize before everything is shutdown. An example of thisfrom occuring. This state only occurs if the enable pin is de-operation can be seen below:
asserted after the completion of timer 1, but before the entirepower-up sequence is completed.
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Incomplete Sequence
All the internal timers are generated by a master clock thatmately 400 µs to timers 1 and 4 which is a result of thehas an extremely low tempco. This allows for tight accuracyEPROM refresh. This refresh time is in addition to the pro-across temperature and a consistent ratio between the indi-grammed delay time and will be almost insignificant to all butvidual timers. There is a slight additional delay of approxi-the shortest of timer delays.
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LM3880CUSTOM SEQUENCER
The LM3880 Power Sequencer is based on a CMOS processutilizing an EPROM that has the capability to be custom pro-grammed at the factory. Approximately 500,000,000 differentoptions are available allowing even the most complex systemto be simply sequenced. Because of the vast options that arepossible, customization is limited to orders of a certain quan-Timer Options 1
024681012141618202224262830
All times listed are in milliseconds
tity. Please contact National Semiconductor for more infor-mation.
The variables that can be programmed include the six delaytimers and the reverse sequence order. For the timers, eachcan be individually selected from one of the timer selectorcolumns in the table shown below. However, all six time de-lays must be from the same column.
Timer Options 3
061218243036424854606672788490
Timer Options 4
081624324048566472808896104112120
Timer Options 2
04812162024283236404448525660
The sequencing order for power up is always controlled bylayout. The flag number translates directly into the sequenceorder during power up (ie FLAG1 will always be first). How-ever, for some systems a different power down order couldbe required. To allow flexibility for this aspect in a design, the
Power Sequencer incorporates six different options for con-trolling the power down sequence. These options can be seenin the timing diagrams on the next page. This ability can beprogrammed in addition to the custom timers.
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LM3880Power Down Sequence Options
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LM3880Physical Dimensions inches (millimeters) unless otherwise noted
SOT23-6 Package
NS Package Number MF06A
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LM3880 Power SequencerNotes
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