Single chip multiprocessor architecture with inter

专利名称：Single chip multiprocessor architecture with

internal task switching synchronization bus

发明人：Michael D. Rostoker,Douglas B. Boyle申请号：US08/643263申请日：19960503公开号：US05761516A公开日：19980602

摘要：A plurality of processors which can be the same or different are formed on asingle integrated circuit chip together with a memory controller and an I/O controller,and are interconnected by a data transfer bus. The processors can have larger wordlengths and operate at higher speeds than comparable single chip processors due toreduced latency and signal path lengths. The processors are further interconnected by aprocessor synchronization bus which enables one processor to cause another processorto perform a task by generating an interrupt and passing the required parameters. Theparameters can be passed via shared memory, or via a bidirectional data section of theprocessor synchronization bus. A processor running a large scale CAD or similarapplication can cause a smaller processor to perform I/O tasks in native code. Amultiprocessor system can be configured as including a Single-Chip module (SCM), aMulti-Chip Module (MCM), Board-Level Product (BPL), or as a box-level product whichincludes a power supply.

申请人：LSI LOGIC CORPORATION

代理机构：Oppenheimer Wolff & Donnelly LLP

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