Methods for fabricating integrated circuits with i

专利名称：Methods for fabricating integrated circuits

with improved patterning schemes

发明人：Xiang Hu,Taejoon Han,Hui Peng Koh申请号：US14019155申请日：20130905公开号：US08940641B1公开日：20150127

专利附图：

摘要：Methods for fabricating integrated circuits with improved patterning schemesare provided. In an embodiment, a method for fabricating an integrated circuit includesdepositing an interlayer dielectric material overlying a semiconductor substrate. Further,

the method includes forming a patterned hard mask overlying the interlayer dielectricmaterial. Also, the method forms an organic planarization layer overlying the patternedhard mask and contacting portions of the interlayer dielectric material. The methodpatterns the organic planarization layer using an extreme ultraviolet (EUV) lithographyprocess. The method also includes etching the interlayer dielectric material using thepatterned hard mask and organic planarization layer as a mask to form vias in theinterlayer dielectric material.

申请人：GLOBALFOUNDRIES, Inc.

地址：Grand Cayman KY

国籍：KY

代理机构：Ingrassia Fisher & Lorenz, P.C.

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