© A MIPS R4400 RISC Microprocessor Multichip
©The Aeroflex “RISC TurboEngine”
Module
(Preliminary Data Sheet, use with “MIPS R4000 Microprocessor Users Manual”© MIPS 1993)
Aeroflex Circuit Technology
35 South Service Road, Plainview NY 11803Tel:(516) 694-6700, Fax:(516) 694-6715
1.0 Description
The Aeroflex Circuit Technology “RISC TurboEngine” is a full military temperature range 64 bit, super-pipelined RISC microprocessor with 1M Byte of secondary cache memory packaged in a high speed multichip module (MCM). The module contains the following components:
•(1) R4400SC/MC, a 3.3V powered RISC microprocessor.•(11) SRAMs, 64K by 16.
•(3) Buffers and (3) Passive components for phase lock loop operation.
A Primary cache only version, the R4400PC is also available in the same package or 179 pin PGA
2.0 Flat Package Outline
“F10” Package2.525 MAX 85 Spaces at 0.025 Pin 226Pin 227Pin 141Pin 14053 Spaces at 0.025 R4400PC/SC MCM1.768 MAX .010 Pin 280Pin 1.072 ±.01Pin 87Pin 86.175 MAX .006 Note: Outside ceramic tie bars not shown for clarity. Contact factory for details1
SCD4430 Rev A 11/18/96
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3.0 Electrical Features
•Low power dissipation, 3.3 Volt powered, 64 bit superpipelined RISC R4400 microprocessor- Highly integrated CPU with integer unit, FPA, MMU, I&D cache- Balanced integer & floating point performance- Exploits 2-level instruction-level parallelism- No issue restrictions on the instructions used•Integer unit
- 32 entry, 64 bit wide register - ALU
- Dedicated multiplier/divider
•Super pipelined FPA
- 32/16 entry 32/64 bit register file in a 32 bit mode- 32 entry 64 bit register file in 64 bit mode- Supports single and double precision.- Supports ANSI/IEEE Standard 754-1985
•Memory management unit
- 48 entry TLB for fast virtual-to-physical address translation, software managed cntrl regstrs- Programmable page sizes from 4K bytes to 16M bytes - Total physical address space encompasses 64G bytes
- One pair of pages per TLB entry, each programable in size from 4K bytes to 16M bytes
•JTAG boundary scan capability for testing module interconnects.
•Internal 1M byte secondary cache SRAM configured as a split cache with instruction and data sections sepa-rate. Can be factory configured as unified.
•Provides 16 bit ECC on secondary cache data line, 7 bit ECC on tag line.•Minimum clock rate 50 mHz with no wait states.
•+3.3 Volt P.S.(10 Watts Max.power dissipation) operation is standard.
4.0 Mechanical Features
•Small sizes, 2.5”L X 1.75”W X 0.175”H, 280 pin surface mount flat package or alternate 1.86”LX1.86”W X 0.145”H, 179 pin PGA Package.
•Full military operating temperature range of -55 °C to +125 °C, case temperature
•Designed to meet military specifications, manufactured and tested in Aeroflex’s MIL-PRF-38534 certified facility.
2
SCD4430 Rev A 11/18/96
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5.0 INTERNAL BLOCK DIAGRAM(SC Version)
SCData(127:0)SCDchk(15:0) CEOEDQ143-DQ0(9) 64Kby 16SRAMsA0SCAddr0SCDCSSCOEINTEGER EXECUTION UNITGeneral RegistersALU/Multiply/DividePipeline/ControlCACHE/MMU16K Byte16K ByteInstructionDataCacheCacheCacheControlMMUDATA/INSTRUCTIONCACHEA14:A1WEBWHA15BWLGNDSCAddr(14:1)48 EntryTLBSystemInterfaceFLOATING POINTFPU ALUBWHBWLA15(2) 64Kby 16SRAMsOECACHE TAGA14:A1WECEA0DQ0-DQ31SCTag(24:0)SCTchk(6:0)SCAddr17Multiply/DivideSquare RootFP RegisterPipeline ControlR4400SC/MC MicroprocessorSCTCSSCWE3
SCD4430 Rev A 11/18/96
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6.0 Module Symbolic Interface Connections
R4400MultichipModule
22
TClock(1:0)RClock(1:0)MasterClockMasterOutSyncOutSyncInIOOutIOInFault*VccPVssP
Status(7:0)VccSenseVssSense
JTDIJTDOJTMSJTCK
Clock/Control InterfaceVccGnd
8Note: Int(5:1)* available on R4400PC version ‡ IvdAck, IvdErr used in “MC” mode
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SCD4430 Rev A 11/18/96
PowerJTAGInterfaceSysAD(63:0)SysAD(7:0)SysCmd(8:0)SysCmdPValidIn*ValidOut*ExtRqst*Release*RdRdy*WrRdy*IvdAck* ‡IvdErr* ‡
6489
5
Int(5:1)*Int0*NMI*
System InterfaceModeClockModeInVCCOkColdReset*Reset*256K/1M*
Initialization InterfaceInterruptInterface元器件交易网www.cecb2b.com
7.0 Signal Descriptions
System Interface Signals
SysAD(63:0)
I/O
System address/data bus: A 64 bit address and data bus for communication between the processor and an external agent
System address/data check bus: An 8 bit bus contain-ing check bits for the SysAD bus
System command/identifier bus parity: A 9 bit bus for command and data identifier transmission between the processor and an external agent
System command /data identifier bus parity: A single, even parity bit for thr SysCmd bus
Valid Input: An external agent asserts ValidIn* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus Valid Output: The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SYSCMD busExternal Request: An external agent asserts ExtRqst* to request the use of the system interface. The processor grants the request by asserting Release*
Release Interface: In response to the assertion of ExtRqst*, the processor asserts Release* to signal the requesting device that the system interface is availableRead ready: The external agent asserts RdRdy*to indi-cate that it can accept processor read, invalidate, or update requests in both overlap and non-overlap mode or can accept a read followed by a potential invalidate or update request in the overlap mode
Write ready: An external agent asserts WrRdy* when it can accept a processor write request
Invalidate acknowledge: An external agent asserts IvdAck* to signal successful completion of a processor invalidate or update request (MC only)
Invalidate error: An external agent asserts InvErr* to signal unsuccessful completion of a processor invali-date or update request(MC only)
SysADC(7:0)SysCmd(8:0)
I/OI/O
SysCmdPValidin*
I/O I
ValidOut* O
ExtRqst* I
Release* O
RdRdy* I
WrRdy*IvdAck*
I I
IvdErr* I
5
SCD4430 Rev A 11/18/96
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Clock/Control Interface Signals
TClock(1:0)RClock(1:0)MasterClockMasteroutSyncOut
O O I O O
Transmit clocks : Two identical transmit clocks that establish the system interface frequency
Receive clocks: Two identical receive clocks that estab-lish the system interface frequency
Master clock: Master clock input establishes the pro-cessor operating frequency
Master clock out: Master clock output aligned with MasterClock
Synchronization clock out: Synchronization clock out-put must be connected to SyncIn through an intercon-nect that models the interconnect between MasterOut, TClock, RClock, and the external agent.
Synchronization clock in: Synchronization clock input I/O output: Output slew rate control feedback loop out-put. Must be connected to IOIn through a delay loop that models the I/O path from the processor to an external agent.
I/O input: Output slew rate control feedback loop input (see IOOut)
Fault: The processor asserts Fault to indicate a mis-match output of boundry comparators
Quiet Vcc for the PLL: Quiet Vcc for the internal phase lock loop
Quiet Vss for the PLL: Quiet Vss for the internal phase lock loop
Status: An 8 bit bus that indicates the current operation status of the processor
Vcc sense: This is a special pin used for testing and characterization. The voltage at this pin directly shows the behavior of the on chip Vcc.
Vss sense: VssSense provides a separate, direct connec-tion fron the on-chip Vss node to a package pin without attaching to the in-package ground planes. VssSence should be connected to Vss in functional system designs.
SyncInIOOut I O
IOInFault*VccPVssPStatus(7:0)VccSense
I O I I OI/O
VssSenseI/O
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SCD4430 Rev A 11/18/96
元器件交易网www.cecb2b.com
Interrupt Interface Signals: These signals comprise the interface used by
external agents to interrupt the R4400 processorInt(5:1)*
I
Interrupt: Five of six general processor interrupts, bit-wise ORed with bits 5:1 of the interrupt register. This feature available on the R4400PC version only
Interrupt: One of six general processor interrupts, bit wise ORed with bit 0 of the interrupt register
Nonmaskable interrupt: Nonmaskable interrupt ORed with bit 6 of the interrupt register
Int0*NMI*
I I
Initialization Interface: These signals comprise the interface by which an external agent initializes the R4400 operating parameters.
ColdReset*
I
Cold Reset: This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of ColdReset*. ColdReset must be de-asserted synchronously with MasterOut.
Boot Mode Clock: Serial boot-mode data clock output at the system clock frequency divided by 256Boot mode data in: Serial boot-mode data input.Reset: This signal must be asserted for any reset sequence. It may be asserted synchronously or asyn-chronously for a cold reset, or synchronously to initate a warm reset. Reset must be de-asserted synchronously with MasterOut.
Vcc is OK: When asserted, this signal tells the R4400 that the 3.3 Volt power supply has been above 3.15 Volts for more than 100 milliseconds & will remain sta-ble . Assertion of VccOK starts initialization sequence.Cache size Select: Must be connected to ground to enable the full 1M Byte of cache. Cache size will be 256K if pin is left unconnected.
JTAG data in: Data is serial, scanned in thru this pinJTAG clock input:The processor outputs a serial clock on JTCK. On the rising edge of JTCK, both JTDI and JTMS are sampled.
JTAG data out: Data is serial, scanned out thru this pin JTAG: JTAG command signal indicates that the incom-ming serial data is command clear.
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SCD4430 Rev A 11/18/96
ModeClockModeInReset*
OII
VccOkI
256K/1M*I
JTAG Interface Signals
JTDIJTCK
II
JTDOJTMSOI
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R4400SC/MC Microprocessor Multichip Module Pinouts Pin #1234567891011121314151617181920212223242526272829303132333435363738394041424344454647FunctionTClock 0VssSys AD 45VssTClock 1VssSys AD 13VssSys AD 14VccJTMSVccSys AD 46VccJTDOVccSys AD 15VccSys AD 47VssStatus 0VccJTDIVssSys ADC 1VccSys ADC 5VccStatus 2VccStatus 1VccJTCKVssSync In VssVss SenseVssVcc SenseVssMasterClockVssStatus 3VccIvdErr*VccStatus 4Pin #4849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394Function VssVssPVccIvdAck*VssVccPVccStatus 5VssStatus 6VccStatus 7VccSys ADC 7VccSys ADC 3VccVCC OkVccSys AD 63VssMasterOutVssSys AD 31VccSys AD 30VccSys AD 62VssSync OutVssSys AD 29VssRClock 1VssSys AD61VssRClock 0VssVccReset* VccSys AD 60VssSys AD 28VccCold_Reset*Pin #9596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141Function VssSys AD 59VccSys AD 27VssIO InVccSys AD 58VssSys AD 26VccIO OutVssSys AD 57VccSys AD 25VssGRPRUN 7VccSys AD 56VssSys AD 24VccGRPSTALL 3VssSys ADC 6VccSys ADC 2VssNMI*VccSys AD 55VssSys AD 23VccRelease * VssSys AD 22VccSys AD 54VssMode In VccRd Rdy *VssSys AD 53Sys AD 217 Do not connect, factory test only , 3 Connect to +V Volts
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SCD4430 Rev A 11/18/96
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R4400SC/MC Microprocessor Multichip Module Pinouts Function Pin #FunctionPin #Vss189Int 4*236Ext RQST*190Vcc237Vcc191Int 5*238Sys AD 52192Vss239Vss193Vcc240Valid Out*194256K/1M*241Vcc195SPARE242Sys AD 20196SPARE243Vss197SPARE244Sys AD 19198CASE GROUND245Vcc199Vss246Sys AD 51200Sys AD 32247Vss201Vcc248ValidIn* 202Sys AD 0249Vcc203Vss250Sys AD 18204Sys AD 1251Vss205Vcc252Sys AD 50206Sys AD 33253Vcc207Vss254InTO* 208Sys AD 34255Vss209Vcc256Sys AD 49210Sys AD 2257Vcc211Vss258Sys AD 17212Sys Cmd 0259Vss213Vcc260Sys AD 16214Sys AD 35261Vcc215Vss262Sys AD 48216Sys AD 3263Vss217Vcc264SPARE 218Sys AD 4265SPARE219Vss266SPARE220Sys Cmd 1267SPARE221Vcc268SPARE222Sys AD 36269SPARE223Vss270SPARE224Sys Cmd 2271Vss225Vcc272InT1*226Sys AD 5273Vcc227Sys AD 37274InT2*228Vss275Vss229Mode Clock276SPARE230Vcc277SPARE231WR RDY* 278InT3*232Vss279SPARE233Sys AD 6280SPARE234VccVss235Sys AD 38Pin #142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188Function VssSys Cmd 3VccSys AD 7VssSys AD 39VccSys Cmd 4VssSys ADC 0VccSys ADC 4VssSys Cmd 5VccSys AD 8VssSys AD 40VccSys Cmd 6VssSys AD 9VccSys AD 41VssSys CMD 7VccSys AD 10VssSys AD 42VccSys Cmd 8VssSys AD 11VccSys AD 43VssSys Cmd P VccSys AD 12VssSys AD 44VccFault*Vss9
SCD4430 Rev A 11/18/96
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R4400PC — PGA — Pinouts (See Alternate Package Figure)FunctionColdresetExtRqstFaultReserved VccIOInIOOutInt0IntlInt2Int3Int4lnt5JTCKJTDIJTDOJTMSMasterClockMasterOutModeClockModeInNMIPLLCap0PLLCap1RClock0RClocklRdRdyReleaseResetSyncInSyncOutSysADOSysAD1SysAD2SysAD3SysAD4SysAD5SysAD6SysAD7SysAD8SysAD9SysAD10SysAD11SysAD12SysAD13Pin #T14U2B16U10T9T13U12N2L3K3J3H3F2H17G16F16E16J17P17B4U4U7........T17R16T5V5U16J16P16J2G2ElE3C2C4B5B6B9B11C12B14B15C16FunctionSysAD14SysAD15SysAD16SysAD17Syr.AD18SysAD19SysAD20SysAD21SysAD22SysAD23SysAD24SysAD25SysAD26SysAD27SysAD28SysAD29SysAD30SysAD31SysAD32SysAD33SysAD34SysAD35SysAD36SysAD37SysAD38SysAD39SysAD40SysAD41SysAD42SysAD43SysAD44SysAD45SysAD46SysAD47SysAD48SysAD49SysAD50SysAD51SysAD52SysAD53SysAD54SysAD55SysAD56SysAD57SysAD58Pin # D17EIBK2M2PiP3T2T4U5U6U9UllT12U14U15T16R17M16H2G3F3D2C3B3C6C7C10C11B13A15C15B17E17F17L2M3N3R2T3U3T6T7T10T11U13FunctionSysAD59SysAD60SysAD61SysAD62SysAD63SysADC0SysADC1SysADC2SysADC3SysADC4SysADC5SysADC6SysADC7SysCmd0SysCmd1SysCmd2SysCmd3SysCmd4SysCmd5SysCmd6SysCmd7SysCmd8SysCmd9TClock0TClocklVCCOkValidInValidOutWrRdyVccPVssPVccVccVccVccVccVccVccVccVccVccVccVccVccVccPin # V15T15U17N16N17C8G17T8L16B8H16U8L17E2D3 B2A5B7C9B10B12C13C14C17D16M17P2R3C5K17K16A2A4A9A11A13A16B18C1D18FlG18HlJ18K1FunctionVccVccVccVccVccVccVccVccVccVccVccVccVccVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssVssPin # L18M1N18R1T18UlV3V6V8V10V12V14V17A3A6A8A10A12A14A17A18B1C18D1F18GIH18J1K18LlM18NlP18R18TlU18V1V2V4V7V9V11V13V16V1810
SCD4430 Rev A 11/18/96
元器件交易网www.cecb2b.com
ORDERING INFORMATION
Microprocessor Module Description
R4430 Primary Cache, +3.3 Volt P.S. Flat PackageR4430 Primary Cache, +3.3 Volt P.S. PGA PackageR4430 1Meg Secondary Cache, +3.3 Volt P.S. Flat Package
Part NumberR4430PC F10 MCMR4430PC P10 MCMR4430SC 1M F10 MCM
Alternate Package Figure — R4400PC — PGA 179 Pins
“P10” Package
Bottom View
4
5
6
7
8
9101112131415161718
Side View
1VUTRPNMLKJHGFEDCBA
23
.100BSC1.7001.840BSC1.880.0181.700BSC1.8401.880.050.221MAXSpecification subject to change without notice
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SCD4430 Rev A 11/18/96
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