Process for fabricating a semiconductor integrated

专利名称：Process for fabricating a semiconductor

integrated circuit

发明人：Toshiyuki Ohkoda,Satoru Kaneko申请号：US07/922065申请日：19920729公开号：US05395782A公开日：19950307

摘要：A LOCOS film is formed on the surface of an epitaxial layer. A gate electrode isformed on the epitaxial layer. At the same time that the gate electrode is formed, alower electrode is formed on the LOCOS film. A diffusion region is formed on eachelement and then covered with a BPSG film. A contact hole and capacitor exposure areformed in a capacitor element simultaneously. A film of SiN is deposited in layers overthe capacitor exposure. The film of SiN covers undesired areas about the capacitorexposure. Excess SiN film outside the desired area over the capacitor exposure isremoved by masking and etching to leave the remaining film area over the capacitorexposure to serve as a capacitor dielectric film. Finally, an Al upper electrode is formedover the SiN film to serve as electrode wiring. The process reduces the series resistanceof the capacitor element, thereby reducing power required for charging the dielectric,and speeding the charging process. The low resistance eliminates parasitic leakagecurrents and the formation of parasitic capacitances.

申请人：SANYO ELECTRIC CO., LTD.

代理人：Vineet Kohli,Thomas R. Morrison

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