MT29F2G08AABWP/MT29F2G16AABWPMT29F4G08BABWP/MT29F4G16BABWPMT29F8G08FABWPFeatures
Figure 1:
48-Pin TSOP Type 1
•Organization:•Page size:
x8: 2,112 bytes (2,048 + 64 bytes)x16: 1,056 words (1,024 + 32 words)•Block size: 64 pages (128K + 4K bytes)
•Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;8Gb: 8,192 blocks•Read performance:•Random read: 25µs
•Sequential read: 30ns (3V x8 only)•Write performance:
•Page program: 300µs (TYP)•Block erase: 2ms (TYP)
•Endurance: 100,000 PROGRAM/ERASE cycles•Data retention: 10 years
•First block (block address 00h) guaranteed to bevalid without ECC (up to 1,000 PROGRAM/ERASEcycles)
•VCC: 2.7V–3.6V
•Automated PROGRAM and ERASE•Basic NAND command set:
•PAGE READ, RANDOM DATA READ, READ ID,READ STATUS, PROGRAM PAGE, RANDOM DATAINPUT, PROGRAM PAGE CACHE MODE, INTER-NAL DATA MOVE, INTERNAL DATA MOVE withRANDOM DATA INPUT, BLOCK ERASE, RESET•New commands:
•PAGE READ CACHE MODE
•READ UNIQUE ID (contact factory)•READ ID2 (contact factory)
•Operation status byte provides a software method ofdetecting:
•PROGRAM/ERASE operation completion•PROGRAM/ERASE pass/fail condition•Write-protect status
•Ready/busy# (R/B#) pin provides a hardwaremethod of detecting PROGRAM or ERASE cyclecompletion
•PRE pin: prefetch on power up•WP# pin: hardware write protect
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__1.fm-Rev. I 1/06 EN
OptionsMarking
•Density:
MT29F2GxxAAB2Gb (single die)
MT29F4GxxBAB4Gb (dual-die stack)
MT29F8GxxFAB8Gb (quad-die stack)
•Device width:
MT29Fxx08xx8
MT29Fxx16xx16
•Configuration: #of # of # of
dieCE#R/B#111A211B422F
A•VCC: 2.7V–3.6V
•Second generation dieB•Package:
48 TSOP type I (lead-free)WP48 TSOP type I (NEW version,WA
8Gb device only, lead-free)48 TSOP type I (contact factory)WG•Operating temperature:Commercial (0°C to 70°C)NoneExtended temperature (-40°C to +85°C)ET
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash MemoryBus OperationPower-On AUTO-READ
During power-on, with the PRE pin at VCC, 3V VCC devices automatically transfer the first page of the memory array to the data register without requiring a command or address-input sequence. As VCC reaches approximately 2.5V, the internal voltage detec-tor initiates the power-on AUTO-READ function.
R/B# will stay LOW (tRPRE) while the first page of data is copied into the data register. See Table18 on page41 for the tRPRE value. Once the READ is complete and R/B# goes HIGH, RE# can be pulsed to output the first page of data.
The PRE function is not supported on extended-temperature devices.
Figure 16: First Page Power-On AUTO-READ (3V VCC only)
≈ 2.5V1VccCLECE#WE#ALEPREtRPRER/B#RE#I/Ox1st2nd3rd.....n thUndefinedNotes:1.Verified per device characterization; not 100 percent tested on all devices.
2.The PRE function is not supported on extended-temperature devices.
Figure 17: AC Waveforms During Power Transitions
3V device: ≈ 2.5VVccHIGHWP#3V device: ≈ 2.5VWE#10µsR/B#Don't CarePDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm-Rev. I 1/06 EN
Undefined 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash MemoryCommand DefinitionsPDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm-Rev. I 1/06 EN
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash MemoryCommand DefinitionsPROGRAM Operations
PROGRAM PAGE 80h-10h
Micron NAND Flash devices are inherently page-programmed devices. Within a block, the pages must be programmed consecutively from the least significant bit (LSB) page of the block to most significant bit (MSB) pages of the block. Random page address pro-gramming is prohibited.
Micron NAND flash devices also support partial-page programming operations. This means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming oper-ations are allowed before an erase is required.
SERIAL DATA INPUT 80h
PAGE PROGRAM operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by five ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The internal write state machine automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects “1s” that are not suc-cessfully written to “0s.”
R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS REGISTER (70h) command and the RESET (FFh) command are the only commands valid during the programming operation. Bit 6 of the status register will reflect the state of R/B#. When the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed. (See Figure23.) The command register stays in read status register mode until another valid command is written to it.
RANDOM DATA INPUT 85h
After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-mand can be used any number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure24 for the proper command sequence.Figure 23: PROGRAM and READ STATUS Operation
tPROGR/B#I/Ox80hAddress (5 cycles) DIN10h70hStatusI/O 0 = 0 PROGRAM successfulI/O 0 = 1 PROGRAM errorFigure 24: RANDOM DATA INPUT
tPROGR/B#I/Ox80hAddress (5 cycles)DIN85hAddress (2 cycles)DIN10h70hStatusPDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm-Rev. I 1/06 EN
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash MemoryCommand DefinitionsPROGRAM PAGE CACHE MODE 80h-15h
Cache programming is actually a buffered programming mode of the standard PAGE PROGRAM command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by five cycles of address, and a full or partial page of data. The data is initially copied into the cache register, and the CACHE WRITE (15h) command is then latched to the command register. Data is transferred from the cache register to the data register on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be controlled by the actual programming time. The first time through equals the time it takes to transfer the cache register contents to the data register. On the second and sub-sequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h) command to determine when the cache register is ready to accept new data. The R/B# pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-ming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the program sequence must use the PROGRAM PAGE (10h) command instead of the
CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete. (See Figure25.)
Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-tion is returned with bit 0 of the status register when bit 5 of the status register is a “1” (ready state). (See Figure25.)
Figure 25: PROGRAM PAGE CACHE MODE Example
tCBSYtCBSYtCBSYtLPROG1R/B#I/Ox80hAddress/Data Input15h80hAddress/Data Input15h80hAddress/Data Input15h80hAddress/Data Input10hA: Without status readstCBSYtLPROG1R/B#Address/Data InputStatus2OutputAddress/Data Input Status2OutputI/Ox80h15h70h80h10h70hB: With status readsNotes:1.See Note 3, Table19 on page41.
2.Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW orpulse multiple times after a 70h command.
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm-Rev. I 1/06 EN
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