专业： ********* 班级：******* 学号：*********姓名：***** 实验地点： ******* 实验时间： ******* 指导教师：*****
一、实验目的：
(1) 理解交通灯控制器的工作原理。
(2) 掌握综合运用VHDL语言进行设计应用系统的能力。
二、实验条件：
（1）每2位同学为1组，每组一台PC机、一台MJU-CS/Altera实验仪。 （2）配套的软硬件设备：并口JTAG下载线、Quartus II 7.2安装程序等。
三、实验内容：
用VHDL语言实现交通灯控制器。
设计任务如下：设计一个十字路口交通灯控制器，如图1所示。
B方向A方向 图1：交通灯示意图
A方向和B方向分别设置左拐、绿、黄和红四盏灯，以及倒计时显示器，用于指挥车辆和行人有序地通行。左拐灯亮表示左转车辆可以通行；绿灯亮表示直行车辆可以通行；黄灯亮表示左转和直行车辆即将禁行；红灯亮表示左转和直行车辆禁行；倒计时显示器用来显示允许通行或禁止通行的时间。
四、实验记录：
（一）理解设计需求
设计要求如下：
1.在十字路口A和B两个方向各设一组左拐、绿灯、黄灯、红灯。显示顺序是：左拐、绿灯、黄灯、红灯。
2、在A和B两个方向各设一组倒计时显示器。A方向左拐、绿灯、黄灯、红灯的显示时间分别为15s、40s、5s、55s。B方向左拐、绿灯、黄灯、红灯的
显示时间分别是15s、30s、5s、65s。
3、控制器有5种工作方式。可通过方式开关的控制进行切换。其中，前4种方式用于特殊情况，第5种方式为正常情况下的工作方式。
3.1 A方向左拐长时间亮，B方向红灯亮，允许A方向左转车辆通行。 3.2 A方向绿灯长时间亮，B方向红灯亮，允许A方向车辆直行。 3.3 B方向左拐长时间亮，A方向红灯亮，允许B方向左转车辆通行。 3.4 B方向绿灯长时间亮，A方向红灯亮，允许B方向车辆直行。 3.5 自动工作方式，两个方向的灯按显示顺序，交替循环显示。 4、控制器设有工作方式状态显示，以指示系统运行的状态。 5、系统设有总复位开关，可在任意时间内对系统进行复位。
（二）画出系统框架，进行功能分割方便模块化设计
1、根据设计要求和系统所具有的功能，交通灯控制器系统框图如图2所示，该系统主要有控制电路模块、译码驱动电路模块、计时模块、扫描显示电路模块构成。其中CLR为系统总复位信号，M2~M0为系统工作方式设置输入信号，CLK为秒脉冲信号，A~G显示的段码输出，SEL5~SEL0为数码管的位码输出，al,ay,ag,ar分别表示A方向的显示灯，bl,by,bg,br分别表示B方向的显示灯。控制电路根据M2~M0信号产生系统控制方式，用于控制其他部分协调工作。
alayagarCLRM2M1M0控制电路译码驱动电路blbybgbrCLK计时电路扫描显示电路A-GSEL5-SEL0 图2 交通灯控制器系统框图
（三）模块化设计各功能
1.计时电路，按照交通灯的亮灯时间和亮灯顺序，设定A和B两个方向计时器的初值，以及在秒脉冲CLK的作用下进行减1计数，并为扫描显示电路提供倒计时时间。
2.扫描显示电路：对计时电路的输出计时信号进行选通、译码，实现倒计时的动态显示。
3.译码驱动电路：根据控制电路的控制信号驱动交通灯的显示。 （四）系统仿真
分模块进行仿真，分析是否符合设计要求。 （五）下载验证
实验中配合示波器观察输出时钟信号。观察现象并记录，分析是否符合设计。
代码:
计时模块的设计: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_time is
port(clk,clr:in std_logic;
m,s:in std_logic_vector(2 downto 0); at,bt:out std_logic_vector(7 downto 0)); end jtd_time;
architecture jtd_2 of jtd_time is
signal ati,bti: std_logic_vector(7 downto 0); signal art,agt,alt,abyt:std_logic_vector(7 downto 0); signal brt,bgt,blt:std_logic_vector(7 downto 0); begin
art<=x\"55\"; agt<=x\"40\"; alt<=x\"15\"; abyt<=x\"05\"; brt<=x\"65\"; bgt<=x\"30\"; blt<=x\"15\"; process(clk,clr,m,s) begin
if clr='1' then ati<=x\"01\";bti<=x\"01\"; elsif (clk'event and clk='1') then if m=\"000\" then ati<=x\"01\";
end if;
if m=\"001\" then ati<=x\"01\"; bti<=x\"06\"; end if;
if m=\"010\" then ati<=x\"41\"; bti<=x\"01\"; end if;
if m=\"011\" then ati<=x\"06\"; bti<=x\"01\"; end if;
if m>=\"100\" then
if (ati=x\"01\")or(bti=x\"01\") then case s is
bti<=x\"51\"; when \"000\"=>ati<=alt;bti<=brt; when \"001\"=>ati<=abyt; when \"010\"=>ati<=agt; when \"011\"=>ati<=abyt;
when \"100\"=>ati<=art; bti<=blt; when \"101\"=>bti<=abyt; when \"110\"=>bti<=bgt; when \"111\"=>bti<=abyt;
when others=>ati<=ati;bti<=bti; end case; end if;
if ati/=x\"01\" then
if ati(3 downto 0)=\"0000\" then ati(3 downto 0)<=\"1001\";
ati(7 downto 4)<=ati(7 downto 4)-1;
else ati(3 downto 0)<=ati(3 downto 0)-1; ati(7 downto 4)<=ati(7 downto 4); end if; end if;
if bti/=x\"01\" then
if bti(3 downto 0)=\"0000\" then bti(3 downto 0)<=\"1001\";
bti(7 downto 4)<=bti(7 downto 4)-1; else bti(3 downto 0)<=bti(3 downto 0)-1; bti(7 downto 4)<=bti(7 downto 4); end if; end if; end if; end if; end process; at<=ati; bt<=bti; end jtd_2;
译码驱动模块的设计: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_light is
port(clr:in std_logic;
m,s:in std_logic_vector(2 downto 0); abl:out std_logic_vector(7 downto 0)); end jtd_light;
architecture jtd_3 of jtd_light is signal lt:std_logic_vector(7 downto 0); begin
process(clr,s,m) begin
if clr='1' then lt<=\"00000000\";
else if m=\"000\" then lt<=\"10000001\"; end if;
if m=\"001\" then lt<=\"00100001\"; end if;
if m=\"010\" then lt<=\"00011000\"; end if;
if m=\"011\" then lt<=\"00010010\"; end if;
if m>=\"100\" then case s is
when \"000\"=>lt<=\"00010100\"; when \"001\"=>lt<=\"10000001\"; when \"010\"=>lt<=\"01000001\"; when \"011\"=>lt<=\"00100001\"; when \"100\"=>lt<=\"01000001\"; when \"101\"=>lt<=\"00011000\"; when \"110\"=>lt<=\"00010100\";
when \"111\"=>lt<=\"00010010\"; when others=>lt<=lt; end case; end if; end if; end process; abl<=lt; end jtd_3;
显示模块的设计: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_dis is
port(clk,clk1k,clr:in std_logic; m1,m2,m0:in std_logic;
at,bt:in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(5 downto 0)); end jtd_dis;
architecture jtd_4 of jtd_dis is
signal ou,stl,sth,mm: std_logic_vector(3 downto 0); signal dis,ds:std_logic_vector(7 downto 0); signal sl:std_logic_vector(2 downto 0); signal sq:std_logic_vector(5 downto 0); begin mm<=\"0\"&m2&m1&m0; sth<=x\"a\";
process(clk1k,clr) begin
if clr='1' then sl<=\"000\";
elsif (clk1k'event and clk1k='1') then if sl=\"101\" then sl<=\"000\"; else sl<=sl+1; end if; end if;
end process; process(sl) begin
case sl is
when \"000\"=>sq<=\"000001\"; when \"001\"=>sq<=\"000010\"; when \"010\"=>sq<=\"000100\"; when \"011\"=>sq<=\"001000\";
when \"100\"=>sq<=\"010000\"; when \"101\"=>sq<=\"100000\"; when others=>null; end case;
end process; process(sl) begin
case sl is
when \"000\"=>ou<=bt(3 downto 0); when \"001\"=>ou<=bt(7 downto 4);
when \"010\"=>ou<=at(3 downto 0); when \"011\"=>ou<=at(7 downto 4); when \"100\"=>ou<=stl; when \"101\"=>ou<=sth; when others=>ou<=x\"0\"; end case;
end process; process(ou) begin
case ou is
when x\"0\"=>ds<=x\"3f\";
when x\"1\"=>ds<=x\"06\"; when x\"2\"=>ds<=x\"5b\"; when x\"3\"=>ds<=x\"4f\"; when x\"4\"=>ds<=x\"66\"; when x\"5\"=>ds<=x\"6d\"; when x\"6\"=>ds<=x\"7d\";
when x\"7\"=>ds<=x\"07\"; when x\"8\"=>ds<=x\"7f\"; when x\"9\"=>ds<=x\"6f\"; when others=>ds<=x\"00\"; end case; end process; process(mm,clk) begin
if mm>=x\"4\" then stl<=x\"5\"; else stl<=mm+1; end if;
if clr='1' then dis<=x\"00\"; elsif mm>=x\"4\" then dis<=ds; elsif sl<\"100\" then
if clk='0' then dis<=ds; else dis<=x\"00\"; end if; else dis<=ds; end if; end process;
led<=dis(6 downto 0); sel<=sq; end jtd_4;
分频模块的设计: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_fp is
port(clk1k:in std_logic; clk:out std_logic); end;
architecture str of jtd_fp is
signal fp : std_logic_vector(9 downto 0); begin
process(clk1k) begin
if (clk1k'event and clk1k='1') then fp<=fp+1; end if; end process; clk<=fp(9); end;
交通灯控制器控制模块的设计: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_ctrl is port(clk,clr:in std_logic;
m:in std_logic_vector(2 downto 0); at,bt:in std_logic_vector(7 downto 0); s:out std_logic_vector(2 downto 0)); end jtd_ctrl;
architecture jtd_1 of jtd_ctrl is
signal q:std_logic_vector(2 downto 0); begin
process(clr,clk,m,at,bt) begin
if clr='1' then q<=\"000\";
elsif (clk'event and clk='1') then if m=\"000\" then q<=\"001\"; end if; if m=\"001\" then q<=\"011\"; end if;
if m=\"010\" then q<=\"101\"; end if;
if m=\"011\" then q<=\"111\"; end if;
if m>=\"100\" then
if (at=\"01\") or (bt=\"01\") then q<=q+1; else q<=q;
end if; end if; end if; end process; s<=q;
end jtd_1;
顶层设计程序: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd is
port(clk1k,clr:in std_logic;
m :in std_logic_vector(2 downto 0); led:out std_logic_vector(6 downto 0); abl:out std_logic_vector(7 downto 0); sel:out std_logic_vector(5 downto 0)); end jtd;
architecture sturcture of jtd is component jtd_time
port(clk,clr:in std_logic;
m,s:in std_logic_vector(2 downto 0);
at,bt:out std_logic_vector(7 downto 0)); end component;
component jtd_light port(clr:in std_logic;
m,s:in std_logic_vector(2 downto 0); abl:out std_logic_vector(7 downto 0)); end component; component jtd_dis
port(clk,clklk,clr:in std_logic; m1,m2,m0:in std_logic;
at,bt:in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(5 downto 0)); end component; component jtd_fp
port(clklk:in std_logic; clk:out std_logic); end component;
component jtd_ctrl
port(clk,clr:in std_logic;
m:in std_logic_vector(2 downto 0); at,bt:in std_logic_vector(7 downto 0); s:out std_logic_vector(2 downto 0)); end component;
signal at,bt:std_logic_vector(7 downto 0); signal s:std_logic_vector(2 downto 0); signal clk:std_logic; begin
U0:jtd_fp
port map(clk1k,clk); u1:jtd_time
port map(clk,clr,m,s,at,bt); u2:jtd_ctrl
port map(clk,clr,m,at,bt,s); u3:jtd_light
port map(clr,m,s,abl); u4:jtd_dis
port map(clk,clk1k,clr,m(1),m(2),m(0),at,bt,led,sel); end sturcture; library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_fp is
port(clklk:in std_logic; clk:out std_logic); end jtd_fp;
architecture str of jtd_fp is
signal fp:std_logic_vector(9 downto 0); begin
process(clklk) begin
if(clklk'event and clklk='1')then fp<=fp+1; end if; end process; clk<=fp(9); end str;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_time is
port(clk,clr:in std_logic;
m,s:in std_logic_vector(2 downto 0);
at,bt:out std_logic_vector(7 downto 0)); end jtd_time;
architecture jtd_2 of jtd_time is
signal ati,bti:std_logic_vector(7 downto 0);
signal art,agt,alt,abyt:std_logic_vector(7 downto 0); signal brt,bgt,blt:std_logic_vector(7 downto 0); begin
art<=x\"55\"; agt<=x\"40\";
alt<=x\"15\"; abyt<=x\"05\"; brt<=x\"65\"; bgt<=x\"30\"; blt<=x\"15\";
process(clk,clr,m,s) begin
if clk='1'then ati<=x\"01\";bti<=x\"01\"; elsif(clk'event and clk='1')then
if m=\"000\"then ati<=x\"01\";bti<=x\"51\"; end if ;
if m=\"001\"then ati<=x\"01\";bti<=x\"06\"; end if ;
if m=\"010\"then ati<=x\"41\";bti<=x\"01\"; end if ;
if m=\"011\"then ati<=x\"06\";bti<=x\"01\"; end if ;
if m>=\"100\"then
if(ati=x\"01\")or(bti<=x\"01\")then case s is
when\"000\"=>ati<=alt;bti<=brt; when\"001\"=>ati<=abyt; when\"010\"=>ati<=agt; when\"011\"=>ati<=abyt;
when\"100\"=>ati<=art;bti<=blt; when\"101\"=>bti<=abyt; when\"110\"=>bti<=bgt; when\"111\"=>bti<=abyt;
when others=>ati<=ati;bti<=bti; end case; end if ; if ati/=x\"01\"then
if ati(3 downto 0)=\"0000\"then ati(3 downto 0)<=\"1001\";
ati(7 downto 4)<=ati(7 downto 4)-1; else ati(3 downto 0)<=ati(3 downto 0)-1; ati(7 downto 4)<=ati(7 downto 4); end if; end if;
if bti/=x\"01\"then
if bti(3 downto 0)=\"0000\"then bti(3 downto 0)<=\"1001\";
bti(7 downto 4)<=bti(7 downto 4)-1; else bti(3 downto 0)<=bti(3 downto 0)-1;
bti(7 downto 4)<=bti(7 downto 4); end if; end if; end if; end if;
end process; at<=ati; bt<=bti; end jtd_2; library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_ctrl is
port(clk,clr:in std_logic;
m:in std_logic_vector(2 downto 0); at,bt:in std_logic_vector(7 downto 0); s:out std_logic_vector(2 downto 0)); end jtd_ctrl;
architecture jtd_1 of jtd_ctrl is
signal q:std_logic_vector(2 downto 0); begin
process(clk,clr,m,at,bt) begin
if clk='1'then q<=\"000\";
elsif(clk'event and clk='1')then if m=\"000\"then q<=\"001\"; end if;
if m=\"001\"then q<=\"011\"; end if;
if m=\"010\"then q<=\"101\"; end if;
if m=\"011\"then q<=\"111\"; end if;
if m>=\"100\"then
if(at=\"01\")or(bt=\"01\")then q<=q+1; else q<=q; end if; end if; end if;
end process; s<=q; end jtd_1; library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_light is
port(clr:in std_logic;
m,s:in std_logic_vector(2 downto 0); abl:out std_logic_vector(7 downto 0)); end jtd_light;
architecture jtd_3 of jtd_light is
signal lt:std_logic_vector(7 downto 0); begin
process(clr,s,m) begin
if clr='1'then lt<=\"00000000\"; elsif m=\"000\"then lt<=\"10000001\"; elsif m=\"001\"then lt<=\"00100001\"; elsif m=\"010\"then lt<=\"00011000\"; elsif m=\"011\"then lt<=\"00100010\"; elsif m>=\"100\"then case s is
when\"000\"=>lt<=\"00010100\"; when\"001\"=>lt<=\"10000001\"; when\"010\"=>lt<=\"01000001\"; when\"011\"=>lt<=\"00100001\"; when\"100\"=>lt<=\"01000001\"; when\"101\"=>lt<=\"00011000\"; when\"110\"=>lt<=\"00010100\"; when\"111\"=>lt<=\"00010010\"; when others=>lt<=lt; end case; else
lt<=\"XXXXXXXX\"; end if;
end process; abl<=lt; end jtd_3; library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity jtd_dis is
port(clk,clklk,clr:in std_logic; m1,m2,m0:in std_logic;
at,bt:in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(5 downto 0)); end jtd_dis;
architecture jtd_4 of jtd_dis is
signal ou,stl,sth,mm:std_logic_vector(3 downto 0); signal dis,ds:std_logic_vector(7 downto 0); signal sl:std_logic_vector(2 downto 0); signal sq:std_logic_vector(5 downto 0); begin
mm<=\"0\"&m2&m1&m0; sth<=x\"A\";
process(clklk,clr) begin
if clr='1'then sl<=\"000\";
elsif(clklk'event and clklk='1')then if sl=\"101\"then sl<=\"000\"; else
sl<=sl+1; end if; end if; end process; process(sl) begin
case sl is
when\"000\"=>sq<=\"000001\"; when\"001\"=>sq<=\"000010\"; when\"010\"=>sq<=\"000100\"; when\"011\"=>sq<=\"001000\"; when\"100\"=>sq<=\"010000\"; when\"101\"=>sq<=\"100000\"; when others=>null; end case; end process; process(sl) begin
case sl is
when\"000\"=>ou<=bt(3 downto 0); when\"001\"=>ou<=bt(7 downto 4); when\"010\"=>ou<=at(3 downto 0); when\"011\"=>ou<=at(7 downto 4); when\"100\"=>ou<=stl; when\"101\"=>ou<=sth; when others=>ou<=x\"0\"; end case; end process; process(ou) begin
case ou is
when x\"0\"=>ds<=x\"3f\"; when x\"1\"=>ds<=x\"06\"; when x\"2\"=>ds<=x\"5b\"; when x\"3\"=>ds<=x\"4f\"; when x\"4\"=>ds<=x\"66\"; when x\"5\"=>ds<=x\"6d\"; when x\"6\"=>ds<=x\"7d\"; when x\"7\"=>ds<=x\"07\"; when x\"8\"=>ds<=x\"7f\"; when x\"9\"=>ds<=x\"6f\"; when others=>ds<=x\"00\"; end case; end process; process(mm,clk) begin
if mm>=x\"4\"then stl<=x\"5\"; else
stl<=mm+1; end if;
if clr='1'then dis<=x\"00\"; elsif mm>=x\"4\"then dis<=ds; elsif sl<=\"100\"then
if clk='0'then dis<=ds; else
dis<=x\"00\"; end if ; else
dis<=ds; end if;
end process;
led<=dis(6 downto 0); sel<=sq; end jtd_4;
六、实验小结：
(1) 基本理解了交通灯控制器的工作原理。
(2) 了解到综合运用VHDL语言进行设计应用系统的难度且掌握此能力还是相当困难的。
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