FM3 Family
32-BIT MICROCONTROLLER
MB9B500 Series
Software Watchdog Timer Setting/Usage
AN706-00007-1v0-E All Rights Reserved.
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AN706-00007-1v0-E Revision History
Rev 1.0
Date Nov 04, 2010
Remark First Edition
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AN706-00007-1v0-E Table of Contents
Revision History....................................................................................................................2 Table of Contents..................................................................................................................3 1 2
Preface..........................................................................................................................4 Software Watchdog Timer..............................................................................................5 2.1 2.2 2.3 2.4 3 3.1 3.2 4
Interrupt (NVIC)......................................................................................................5 Register..................................................................................................................7
WdogIntClr (Software Watchdog Timer Lock Register)...................................8 Software Watchdog Reset......................................................................................8 APB0 Bus Clock.....................................................................................................8 Sample Program....................................................................................................9
Software watchdog underflow cycle in sample program..................................9 Setting Procedure Example..................................................................................10
2.2.1
Setting Example (Sample Program)..............................................................................9 3.1.1
Precautions..................................................................................................................11
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AN706-00007-1v0-E 1
Preface
The watchdog timer is a function to detect runaway of user program. The watchdog timer of this series has following features: The software watchdog timer is activated by user program. A divided clock of APB bus clock is used for a count clock.
It counts cycles while CPU program is operating, and it stops counting while APB clock
of the standby mode (timer mode, stop mode, and during oscillation stabilization wait time of the source clock). The count value is retained so that it continues counting after returning from the standby mode.
The software watchdog timer is stopped by all the resets.
This application note describes how to use the software watchdog timer.
It also shows setting example of changing the count value of software watchdog timer to an arbitrary value in sample program (in the case of MB9BF506).
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AN706-00007-1v0-E 2 Software Watchdog Timer
Note: For features, operations, block diagrams of software watchdog timer, refer to CHAPTER 11: Watchdog timer of MB9Axxx/MB9Bxxx Series PERIPHERAL MANUAL. 2.1
Interrupt (NVIC)
Table 2-1 shows vectors of exception and interrupt factor input to NVIC.
Note: For detail on NVIC, refer to CHAPTER 8: Nested Vectored Interrupt Controller of Cortex-M3 Technical Reference Manual.
Table 2-1 Software watchdog timer interrupt vector
Exception and interrupt factor Software watchdog timer
Vector No. 17
Interrupt No.1
Vector Offset 0x44
Note: For all interrupt details and interrupt numbers, refer to 3. Exception and Interrupt Vectors in CHAPTER 6: Interrupts of MB9Axxx/MB9Bxxx Series PERIPHERAL MANUAL.
All interrupts including exceptions of CPU core are controlled by NVIC.
Cortex-M3 Technical Reference Manual defines all exception type IRQs as external interrupt inputs.
This document expresses exception type IRQs as peripheral interrupts. Peripheral interrupts include interrupts from external pins (external interrupts and NMI control block) and interrupts from peripheral resources within the LSI.
NVIC interrupts can be enabled or disabled by writing a value to the bit field of correspondent interrupt enable set register or interrupt enable clear register. These registers are enabled by writing “1” or cleared by writing “1”. Current enable states of correspondent registers can be read from both registers.
Interrupt enable set register is used for the following purposes: To enable a interrupt
To determine which interrupts are currently enabled
Each bit of the registers corresponds to one of 32 interrupts.
Setting a bit of interrupt enable set register enables the correspondent interrupt. When enable bit of the pending interrupt is set, the processor activates the interrupt according to
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AN706-00007-1v0-E the priority.
If the enable bit is cleared, the interrupt will be suspended by asserting interrupt signal. However, this interrupt cannot be activated regardless of the priority.
For this reason, disabled interrupt can be used as general-purpose I/O bit to be latched. Also, this bit can be cleared by reading it without calling an interrupt.
When using the interrupt of software watchdog timer, set “1” to the bit corresponding to No.1 interrupt of interrupt enable set register. Table 2-2 shows the setting of interrupt enable set register.
Table 2-2 Setting of interrupt enable set register
Address: 0xE000E100 = 0bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1X
bit 31 30 29 28 27 26 25 24 23 22 212019181716151413121110987 6 5 4 3 2 10valueXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX1X
Note: “X” is an arbitrary value.
Address: 0xE000E104 = 0b0000000000000000XXXXXXXXXXXXXXXX
bit 31 30 29 28 27 26 25 24 23 22 212019181716151413121110987 6 5 4 3 2 10value 0 0 0 0 0 00 0 0 0 000000XXXXXXXXX X X X X X XX
Note: “X” is an arbitrary value.
The priority of peripheral interrupt after vector No.16 can be set by interrupt priority register. The interrupt priority register is assigned with 4 bits for each interrupt.
Since interrupt priority register of software watchdog timer is interrupt No.1, the address: “0xE000E401” becomes interrupt priority register of software watchdog timer. The register value after a reset is ”0x00”, which is the highest priority.
Also, since vector offset is ”0x44”, the interrupt address will be stored in ”0x00000044”.
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AN706-00007-1v0-E 2.2
Register
Setting registers differs according to hardware and software. Table 2-3 shows the registers that can be set by software watchdog timer.
Note: For details on register setting, refer to CHAPTER 11: Watchdog timer of MB9Axxx/MB9Bxxx Series PERIPHERAL MANUAL.
Table 2-3 Registers used by software watchdog timer
Abbreviation Register name Address* WdogLoad
Software watchdog timer load register
WdogValue
Software watchdog timer value register
WdogControl
Software watchdog timer control register
WdogIntClr
Software watchdog timer clear register
WdogRIS
Software watchdog timer interrupt status register
WdogLock
Software watchdog timer lock register
*: software watchdog timer base address: 0x40012000
+ 0x000
+ 0x004
+ 0x008
+ 0x00C
+ 0x010
+ 0xC00
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AN706-00007-1v0-E
2.2.1 WdogIntClr (Software Watchdog Timer Lock Register)
This lock function is to prevent unauthorized accesses to the registers of software watchdog timer. The lock of software watchdog timer is disabled after a reset. To enable the lock, write the value other than “0x1ACCE551” to WdogIntClr. To release the lock, write “0x1ACCE551” to WdogIntClr.
By reading WdogIntClr, the status of register lock can be checked. The read value while it is locked is “0x01”, and the read value while it is unlocked is “0x00”. 2.3
Software Watchdog Reset
When a reset by software watchdog timer occurs, refer to the reset factor register to confirm it. Table 2-4 shows the conditions and flags.
Table 2-4 Software watchdog reset
Generation factor Release factor Initialization target Flag 2.4
APB0 Bus Clock
The bus clock for software watchdog timer of MB9BF506 is APB0 (refer to Block Diagram of FM3 MB9B500 Series Data Sheet) and its maximum internal operating clock frequency is 40 MHz. When CPU/AHB bus clock is to be set over 40 MHz, you need to divide frequency by setting APB0 prescaler register (APBC0_PSR).
Note: For details on APB0 bus clock, refer to CHAPTER 2: Clock of MB9Axxx/MB9Bxxx Series PERIPHERAL MANUAL.
Initializes all register settings and hardware except the debug circuit and hardware watchdog timer (including control register). Note: The reset factor register is not initialized. Bit 4 (SWDT) of reset factor register (RST_STR) = 1
Generated by two underflows without clearing the counter of software watchdog timer.
Released automatically after issuing a reset.
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AN706-00007-1v0-E 3
3.1
Setting Example (Sample Program)
Sample Program
This section describes the sample program that configures the software watchdog timer. The following shows the setting conditions of this sample program.
Clock conditions:
Set PLL clock of 80 MHz as a master clock (multiply after inputting external main
clock of 4 MHz to X0 and X1)
APB2 prescaler: 1/2 frequency (APB2 bus clock: 40 MHz)
According to the conditions above, process as follows in sample program:
- - -
Set the clock before main loop and then set the software watchdog timer (counter value and watchdog activation)
Clear the hardware watchdog counter for each main loop
If the counter underflows because of abnormal operation, underflow interrupt of software watchdog timer counter is generated to transit to interrupt function. If an underflow is generated again, software watchdog reset will occur.
3.1.1 Software watchdog underflow cycle in sample program
The following shows the software watchdog underflow cycle in sample program. Base clock: PLL clock (multiplied from external main clock of 4 MHz) frequency: 80 MHz APB0 bus prescaler setting: APBC0_PSR = 0x01, clock prescaler: 1/2 APB0 bus clock frequency: 40 MHz → 0.025 μs for 1 cycle Interval cycle of software watchdog timer: WdogLoad = 0x03FFFFFF Count value: 67,108,863
Underflow frequency is calculated as follows:
0.025 μs*67108863 = 1677721.575 μs = 1.677721575 s (hereinafter approx. 1.67 s)
After activating software watchdog timer, underflow interrupt is generated If the software watchdog is not cleared by clear register within 1.67 s after a change of load register and clear by clear register. Moreover, if it is still not cleared by clear register within 1.67 s after this, software watchdog reset is generated.
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AN706-00007-1v0-E 3.2
Setting Procedure Example
=
The following procedure shows the setting of software watchdog timer in sample program.
SW-WDG setting START Note1: SW-WDG represents software watchdog
Set APB0 bus clock division. Set PLL clock as a master clock Unlock all registers (WdogLock 0x1ACCE551 (The read value of WdogLock is “0x00”)) Set a down counter (cycle) (WdogLoad = 0x03FFFFFF) =Enable SW-WDG count/interrupt, Activate SW-WDG timer enable a reset (WdogControl = 0x03)Note2: other than “0x1ACCE551”
Lock SW-WDG register (WdogLock = 0x00000000) Lock SW-WDG register Enable NVIC SW-WDG interrupt Main loop from here Unlock all registers (WdogLock = 0x1ACCE551 (the read value of WdogLock is ”0x00”)) Unlock SW-WDG register Clear counter (WdogIntClr 0x11111111 (arbitrary value)) Lock SW-WDG register (WdogLock = Note3: other than “0x1ACCE551” 0x00000000 (the read value WdogLock is “0x01”)) Lock SW-WDG register
Fig. 3.1 Setting procedure example in sample program
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AN706-00007-1v0-E 4
Precautions
The sample project attached to this application note is created by IAR Embedded
Workbench for ARM.
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