74ACTQ563 Quiet Series™ Octal Latch with 3-STATE OutputsJanuary 1990
Revised December 1998
74ACTQ563
Quiet Series™ Octal Latch with 3-STATE Outputs
General Description
The ACTQ563 is a high speed octal latch with bufferedcommon Latch Enable (LE) and buffered common OutputEnable (OE) inputs. The ACTQ563 is functionally identicalto the ACTQ573, but with inverted outputs. The ACTQ563utilizes Fairchild FACT Quiet Series™ technology to guar-antee quiet output switching and improved dynamic thresh-old performance. FACT Quiet Series features GTO™output control and undershoot corrector in addition to asplit ground bus for superior performance.
Features
sICC and IOZ reduced by 50%
sGuaranteed simultaneous switching noise level anddynamic threshold performancesGuaranteed pin-to-pin skew AC performancesImproved latch-up immunity
sInputs and outputs on opposite sides of package alloweasy interface with microprocessorssOutputs source/sink 24 mA
sFaster prop delays than standard ACT563
sFunctionally identical to the ACTQ573 but with invertedoutputs
Ordering Code:
Order Number74ACTQ563PC
Package Number
N20A
Package Description
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic SymbolsConnection Diagram
Pin Assignment for DIP
IEEE/IEC
Pin Descriptions
Pin NamesD0–D7LEOEO0–O7
Data InputsLatch Enable Input
3-STATE Output Enable Input3-STATE Latch Outputs
Description
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor CorporationDS010631.prfwww.fairchildsemi.com
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74ACTQ563Functional Description
The ACTQ563 contains eight D-type latches with 3-STATEcomplementary outputs. When the Latch Enable (LE) inputis HIGH, data on the Dn inputs enters the latches. In thiscondition the latches are transparent, i.e., a latch output willchange state each time its D input changes. When LE isLOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-sition of LE. The 3-STATE buffers are controlled by theOutput Enable (OE) input. When OE is LOW, the buffersare in the bi-state mode. When OE is HIGH the buffers arein the high impedance mode but that does not interfere withentering new data into the latches.
Function Table
InputsOEHHHHLLL
H = HIGH Voltage LevelL = LOW Voltage LevelX = Immaterial
Z = High ImpedanceNC = No Change
InternalDXLHXLHX
QXHLNCHLNC
Outputs
OZZZZHLNC
Function
LEXHHLHHL
High-ZHigh-ZHigh-ZLatchedTransparentTransparentLatched
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACTQ563 Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)DC Input Diode Current (IIK)VI = −0.5VVI = VCC + 0.5VDC Input Voltage (VI)
DC Output Diode Current (IOK)VO = −0.5VVO = VCC + 0.5VDC Output Voltage (VO)DC Output Sourceor Sink Current (IO)DC VCC or Ground Currentper Output Pin (ICC or IGND)Storage Temperature (TSTG)DC Latchup Sourceor Sink Current
± 300 mA± 50 mA
−65°C to +150°C
± 50 mA−20 mA+20 mA
−0.5V to VCC + 0.5V
−20 mA+20 mA
−0.5V to VCC + 0.5V
−0.5V to +7.0V
Junction Temperature (TJ)PDIP
140°C
Recommended OperatingConditions
Supply Voltage (VCC)Input Voltage (VI)Output Voltage (VO)Operating Temperature (TA)Minimum Input Edge Rate ∆V/∆tVIN from 0.8V to 2.0VVCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damageto the device may occur. The databook specifications should be met, with-out exception, to ensure that the system design is reliable over its powersupply, temperature, and output/input loading variables. Fairchild does notrecommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V0VtoVCC0VtoVCC
−40°C to +85°C
125 mV/ns
DC Electrical Characteristics
SymbolVIHVILVOH
Parameter
Minimum HIGH LevelInput VoltageMaximum LOW LevelInput VoltageMinimum HIGH LevelOutput Voltage
VCC(V)4.55.54.55.54.55.54.55.5
VOL
Maximum LOW LevelOutput Voltage
4.55.54.55.5
IINIOZICCTIOLDIOHDICCVOLPVOLVVIHDVILD
Maximum Input Leakage CurrentMaximum 3-STATELeakage CurrentMaximum ICC/InputMinimum DynamicOutput Current (Note 3)
Maximum Quiescent Supply CurrentQuiet Output
Maximum Dynamic VOLQuiet Output
Minimum Dynamic VOLMinimum HIGH LevelDynamic Input VoltageMaximum LOW LevelDynamic Input Voltage
5.05.0
1.91.2
2.20.8
VV
5.0
−0.6
−1.2
V
5.55.55.55.55.0
1.1
4.01.5
0.6
1.575−7540.0
mAmAmAµAV
5.55.5
0.0010.001TA = +25°CTyp1.51.51.51.54.495.49
2.02.00.80.84.45.43.864.860.10.10.360.36± 0.1± 0.25
TA = −40°C to +85°CGuaranteed Limits
2.02.00.80.84.45.4
VIN = VIL or VIH
3.764.760.10.1
VIN = VIL or VIH
0.440.44± 1.0± 2.5
µAµAV
IOL = 24 mAIOL = 24 mA (Note 2)VI = VCC, GNDVI = VIL, VIHVO = VCC, GNDVI = VCC − 2.1VVOLD = 1.65V MaxVOHD = 3.85V MinVIN = VCC or GNDFigure 1, Figure 2(Note 4)(Note 5)Figure 1, Figure 2(Note 4)(Note 5)(Note 4)(Note 6)(Note 4)(Note 6)V
IOH = −24 mA
IOH = − 24 mA (Note 2)IOUT = 50 µAVUnitsV
Conditions
VOUT = 0.1Vor VCC − 0.1VVOUT = 0.1V
or VCC − 0.1V
V
IOUT = − 50 µA
Note 2: All outputs loaded; thresholds on input associated with output under test.Note 3: Maximum test duration 2.0 ms, one output loaded at a time.Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
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74ACTQ563DC Electrical Characteristics (Continued)
Note 6: Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3V. Input-under-test switching; 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
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74ACTQ563 AC Electrical Characteristics
TA = +25°C
SymboltPHLtPLHtPLHtPHLtPZLtPZHtPHZtPLZtOSHLtOSLH
Output to Output Skew (Note8)Dn to On
Output Disable Time
Parameter
Propagation DelayDn to On
Propagation DelayLE to On
Output Enable Time
VCC(Note 7)3.35.03.35.03.35.03.35.03.35.0
Min2.51.52.52.02.51.51.01.0
CL = 50 pF
Typ8.55.58.56.08.56.09.06.51.00.5
Max11.57.513.08.513.08.514.59.51.51.0
TA = −40°C to +85°C
CL = 50 pFMin2.51.52.52.02.51.51.01.0
Max12.08.013.59.013.59.015.010.01.51.0
nsnsnsnsnsUnits
Note 7: Voltage Range 5.0 is 5.0V ±0.5V and 3.3 is 3.3V ± 0.3V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. Thespecification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
VCC
SymboltStHtW
Parameter
Setup Time, HIGH or LOWDn to LE
Hold Time, HIGH or LOWDn to LE
LE Pulse Width, HIGH
(V)(Note 9)3.35.03.35.03.35.0
Note 9: Voltage Range 5.0 is 5.0V ±0.5V and 3.3V is 3.3 ± 0.3V.
TA = +25°CCL = 50 pFTyp00002.02.0
3.03.01.51.54.04.0
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
3.03.01.51.54.04.0
nsnsnsUnits
Capacitance
SymbolCINCPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ4.542
UnitspFpF
VCC = OPENVCC = 5.0V
Conditions
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74ACTQ563FACT Noise Characteristics
The setup of a noise characteristics measurement is criticalto the accuracy and repeatability of the tests. The followingis a brief description of the setup used to measure thenoise characteristics of FACT.Equipment:
Hewlett Packard Model 8180A Word GeneratorPC-163A Test Fixture
Tektronics Model 7854 OscilloscopeProcedure:
1.Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.2.Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. Thisrequires that the oscilloscope be deskewed first. It isimportant to deskew the HFS generator channelsbefore testing. This will ensure that the outputs switchsimultaneously.3.Terminate all inputs and outputs to ensure proper load-ing of the outputs and that the input levels are at thecorrect voltage.4.Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increaseDUT heating and effect the results of the measure-ment.
VOLP/VOLV and VOHP/VOHV:
•Determine the quiet output pin that demonstrates thegreatest noise levels. The worst case pin will usually bethe furthest from the ground pin. Monitor the output volt-ages using a 50Ω coaxial cable plugged into a standardSMB type connector on the test fixture. Do not use anactive FET probe.
•Measure VOLP and VOLV on the quiet output during theworst case transition for active and enable. MeasureVOHP and VOHV on the quiet output during the worstcase active and enable transition.•Verify that the GND reference recorded on the oscillo-scope has not drifted to ensure the accuracy and repeat-ability of the measurements.VILD and VIHD:
•Monitor one of the switching outputs using a 50Ω coaxialcable plugged into a standard SMB type connector onthe test fixture. Do not use an active FET probe.•First increase the input LOW voltage level, VIL, until theoutput begins to oscillate or steps out a min of 2 ns.Oscillation is defined as noise on the output LOW levelthat exceeds VIL limits, or on output HIGH levels thatexceed VIH limits. The input LOW voltage level at whichoscillation occurs is defined as VILD.•Next decrease the input HIGH voltage level, VIH, untilthe output begins to oscillate or steps out a min of 2 ns.Oscillation is defined as noise on the output LOW levelthat exceeds VIL limits, or on output HIGH levels thatexceed VIH limits. The input HIGH voltage level at whichoscillation occurs is defined as VIHD.•Verify that the GND reference recorded on the oscillo-scope has not drifted to ensure the accuracy and repeat-ability of the measurements.
VOHV and VOLP are measured with respect to ground reference.Input pulses have the following characteristics:f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms5.Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH forAC devices. Verify levels with a n oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ563 Quiet Series™ Octal Latch with 3-STATE OutputsPhysical Dimensions inches (millimeters) unless otherwise noted
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:
2.A critical component in any component of a life support1.Life support devices or systems are devices or systems
device or system whose failure to perform can be rea-which, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life supportbody, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to thewww.fairchildsemi.comuser.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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