专利名称：Method and apparatus for scheduling
memory current and temperaturecalibrations based on queued memoryworkload
发明人：John E. Jenne,Sompong P. Olarig申请号：US09726739申请日：20001130
公开号：US20020065981A1公开日：20020530
专利附图：
摘要：A computer system includes a memory controller that controls and formats
transactions with a high speed memory. The memory controller includes a read queue, awrite queue, and various other queues in which memory transactions may be storedpending execution. The memory controller periodically executes calibration cycles, suchas temperature calibration cycles to the memory to reduce memory errors. Thetemperature calibration cycles may include an idle state during which no readtransactions can be executed. The memory controller includes arbitration logic thatreduces latency by issuing read transaction first. Once reads have been issued, thearbitration logic executes any pending temperature cycles. During the idle period of thecalibration cycle, the arbitration logic schedules write transactions, and transactions tomemory from other queues and devices, including precharge transactions, row activatetransactions, refresh cycles, and other calibration cycles.
申请人：JENNE JOHN E.,OLARIG SOMPONG P.
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